Understanding ARM Assembly, Part 1 | Hacker News Reader

Understanding ARM Assembly, Part 1

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69 pointsrnicholson13 comments

Memories.

If you're interested in this sort of thing there is one book you should read: Arm System on Chip by Steve Furber (original designer of the ARM)

http://www.amazon.com/ARM-System---Chip-Architecture-Edition...

Brings back a lot of memories of assembly programming on the Acorn Archimedes[1] (ARM2 core) back in the early 90s.

It certainly was a revelation (all those registers!) after years of messing around with Z80/6502/80[123]?86.

1. https://en.wikipedia.org/wiki/Acorn_Archimedes

Why does the author refer to IA-32 and x86 as separate architectures? Is there an actual technical distinction or are they aliases for the same thing?

IA-32 is a subset of x86, as x86 includes everything from the 8086 up and IA-32 (often AKA i386) is the 32-bit architecture from the 80386 up. But this doesn't really explain why both were listed there, particularly when listed alongside the 386 as a separate listing.

This was posted two days ago, I found the analysis of a C map function compiled to arm interesting

http://www.reddit.com/r/compsci/comments/1r8izo/what_would_i...

If only there was a tutorial like this, but for the Cortex-M series — specifically, M0+ and M4.

I recently had to dig through tons of documentation just to get started and ARM is really bad at providing overview documentation. As an example: I quickly discovered that the Cortex-M doesn't really have 16 registers. You only get 8 general-purpose registers and 5 kinda-registery-quick-storage-locations, which only certain instructions can access. To this day I couldn't find a clear list of instructions that can access these high registers.

No, they're really all registers; it's just some of them aren't usable with all instructions for some of the M profile cores. Specifically, ARMv6M cores (like the M0) only implement the Thumb1 instruction set (the 16 bit instructions) plus a few additions so they don't need any ARM mode instructions for exception handling etc. ARMv7M cores (like the M3) implement pretty much all of Thumb2, including the 32 bit versions of instructions which allow you to make much greater use of the high registers (at the cost of slightly larger code).

http://infocenter.arm.com/help/topic/com.arm.doc.qrc0006e/QR... is the Thumb 16-bit instruction set quick reference card, which seems to have a reasonable summary of which instructions have which register restrictions.

M3 and M4 are two of the absolute nicest cores to program for. A reasonably orthogonal ISA that's still small enough to fit on one side of a reference card, enough registers, and a wonderfully simple performance model (everything is single-cycle except for multiplies and memory ops).

Thanks, that is very helpful, and I've never seen that reference card until now!

I'm co-authoring a textbook on ARM assembly language that focuses on the M3. It will be finished next year.

That is because those processors are running in thumb mode... essentially using 16-bit opcodes. The original ARM instruction set is 32-bit opcodes which is enough to encode 16 registers. The thumb mode was added to increase code density and subsequently they found it could be used for most common cases.

It's about time.

I was keen to learn ARM a year or two back and I was absolutely horrified at how dismal the documentation ARM provided was. I had problems even finding an assembler; and what I could find was pay-gated (with a price bracket too high as a personal improvement project). It's crazy that these platforms are toted as the future and yet the entry-level developer experience is by far the worst I have ever come across. Are they selling chips or are they selling manuals? /rant

Hopefully ntdebug continues the series.

Nice to see Microsoft encroaching on this territory .. but I already have a pretty good reference on the subject of ARM assembly:

http://www.eng.auburn.edu/~nelson/courses/elec5260_6260/ARM_...

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