Non-Von Neumann Supercomputer in an FPGA | Hacker News Reader

Non-Von Neumann Supercomputer in an FPGA

chrisfenton.com

68 pointsluu10 comments

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There are a few recreations of old supercomputers using FPGA, so it's nice to add this one to the list.

(http://www.chrisfenton.com/homebrew-cray-1a/)

and here are a few more (mostly home computers)

(https://news.ycombinator.com/item?id=4931867)

Dear lord, the comment spam!

Anyway, this architecture is actually quite similar to the design of modern GPUs.

31 small nodes arranged in a binary tree. Communication between parent and children.

cached version: http://web.archive.org/web/20130314085338/http://www.chrisfe...

I'd like to hear more about how these kinds of architectures were programmed. I know about scalar kernels being applied in lockstep across data-parallel arrays. What other patterns were there?

PIC 16F84 is also non-von neumann

Most microcontrollers are. Makes certain bits of design and coding a lot easier. The AVR, some ARM Cortex Ms, etc, share that.

As far as I know, all ARM CPUs are Von Neumann, in that they use the same memory space for instructions and data. The program is often stored in read-only memory (flash), but it's in the same space as SRAM and hardware registers.

AVR, on the other hand, is a Harvard architecture, as the program does not exist in the same address space as data. It is possible to read from program memory, but only using special-purpose instructions. I believe the same goes for PIC, but I'm not as familiar with it.

The description of this machine isn't quite detailed enough for me to say for sure, but I think it may be a Von Neumann architecture, if only because I don't see any labeled instruction memory. I may be misunderstanding how it's supposed to work, though.

The Cortex-M3 and M4 ARMs are Mostly Harvard; just pored through the datasheets to make sure. The first half a gig of address space has a separate bus for code and data, and then has yet another bus for all the memory space above that. They're weird little chips.

It's all the same data and the same address space, though. The first half-gig or so of memory is all flash ROM, so the separate bus just gives the CPU an extra load per cycle (so it can load data from ROM without a wait state). This doesn't make it a Harvard architecture, it just makes it faster.

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