Samsung Starts Mass Producing Industry’s First 3D Vertical NAND Flash
samsung.com
samsung.com
We seem to be in a race to the smallest transistor physically possible, to increase density on 2D chips. Tiny transistors generally leak more heat due to quantum tunnelling, right? So what if the industry moved toward much, much more efficient, larger transistors, layered hundreds or thousands of layers thick in a large 3D architecture? I think the only reason this isn't happening is because it's not really possible to manufacture that sort of chip without it taking a thousand times as long and being a thousand times as likely to fail QA -- but maybe this is a step in that direction.
There were (and may still be) several reasons that 3D was not a regular technology in use. The first was that connecting transistors "across" the chip was done using a metal layer (aluminium at first, later copper) and laying down a metal layer left forced a distance between it and the next silicon layer that you would end up bridging with poly-silicon (NP doped silicon so that it conducts electricity but not as well as metal does). So all of the cross layer connects that weren't metal were slow.
Heat dissipation was another issue for transistors between a 'top' and 'bottom' layer.
Varying feature height, so if transistors were 3 uM thick and resistors were 1uM thick then you put a transistor above a resistor its drain and source layers would be 1uM up from the plane in which the other transistor sits.
Process contamination, basically building a transistor on top of a surface of SIO2 was one thing, but building it on top of another transistor meant than your ion implanting step needed to have really accurate control of depth.
The MEMS revolution gave people a lot more tools that were accurate in depth (vs X & Y position) and regular feature patterns (as opposed to general purpose logic) lend themselves to better 3D planning.
One of Intel's big breakthroughs in 22nM chips was its tri-gate vertical transistor design [1] which allowed the gate area of the transistor to be vertical and thus have enough silicon to hold a reasonable number of electrons.
Short version: The process to make a 2D layer of transistors requires something like 20-30 masking steps, and many of those steps require significant heating. Adding a second plane of 2D transistors on top subjects all of the transistors underneath to more heating, so it is hard to build that structure on top without making the transistors underneath nonfunctional.
This is the first I think I've seen size measured in gigabits, rather than gigabytes, of which there'd be 16, which is still impressive, but on amazon I can buy a 32GB sdcard for $20.
Things like SD cards are really small consumer electronics devices and are spec'd in terms of bytes.
Hopefully, the cost ratios haven't disproportionately increased as well.