Crossbar Resistive RAM stores a terabyte on a chip

They're probably referring to latency, which is very low (30ns). It still is disingenuous, but that's marketing.

Even then the limit is unlikely to come from non-volatile storage itself. The current effective flash R/W speeds are pretty much limited by the controllers.

I remember an article stating that embedded flash controllers typically have a 20MB/s speed limit. This in turn meant that wireless speeds beyond 200Mb/s were mostly worthless, because the devices simply could not utilise any more. If someone can find the article again, I would be delighted.

However: if the reality with RRAM is even half as good as the claims go, then it would certainly encourage the hardware vendors to invest in somewhat better controllers. After all, what good is a new, hyperspeed storage medium if you can't access it any faster than the old one?

It's always been related, but it's not the only factor. Packaging, assembly and test are the other primary components of manufacturing cost. You are correct though, that price (as opposed to cost) is going to include amortized R&D, marketing, license fees, margin etc.

Price or cost?

The whole premise of taking NAND from 25nm to 19nm (for instance) is to fit more floating gates in the same area. You can take that as a smaller die, or as more bits on a slightly larger die than the previous generation.

Die size is indeed a major factor on cost. For a given technology (litho node + process, e.g. # and type of steps), the cost to process a wafer is fairly constant regardless of die size.

If you shrink a die size, you fit more die on a wafer. Additionally, yield goes up (given an independent manufacturing defect density), and especially for large die, the tessellation around the edges has a major impact.

Indirectly, even testing is related to die size, in that there is a limit to tester parallelism, and more gates means more time and more combinatorial patterns to test, e.g. for stuck-at testing.

There are of course non-linear costs in packaging and package-level testing and elsewhere.

Please, be civil. There are better ways to ask a question.

The per unit costs of a chip[1] are essentially constant per wafer. The smaller a chip is, the more of them each wafer will produce. Also, the smaller a chance there is that any given chip will be ruined by an imperfection. So then number of chips you get from each dollar of production cost is a bit less than linearly inversely proportional to the area of the chip. There are other factors too, though, and wafers from more advanced nodes will tend to be more expensive. However, the two examples being compared here were both from the 25nm nod.

[1] Which dominate with memory since production runs tend to be large and the regular patterns make for less design investment than, say, a CPU.

I'm a graphics programmer.

The only reason to prefer the GPU is because it confers an advantage over the traditional CPU+RAM combination. There's nothing inherently special about a modern GPU. The GPU is a sequence of actions and abilities encoded into hardware, e.g. the ability to automatically perform various kinds of texture filtering transparently to the game developer.

Since the GPU is hardware, and since hardware is less flexible than software, a graphics programmer would always prefer a software-based pipeline to a hardware-based one. The reason hardware pipelines are preferred is strictly because their advantages outweigh their disadvantages. Typically, using a GPU enables graphics programmers to create renderers which are 10-100x more efficient than software-based renderers, so the added flexibility of a software rasterizer tends to be forgotten in the face of massive efficiency enabled by the GPU.

The GPU primarily became popular because (a) it offloaded part of the computation from the CPU to dedicated hardware, freeing up the CPU for other tasks like game logic, AI, and more recently physics computations (though nVidia is trying hard to convince developers that hardware-accelerated physics is a viable concept), (b) GPUs increased the amount of available memory, and (c) GPUs dramatically increased the throughput (memory operations per second) of graphics memory.

Memory latency plays a key role in many modern graphics algorithms, such as voxel-based renderers. It's often the case that an algorithm needs to repeatedly cast rays against a voxel structure until hitting some kind of geometry. Therefore, within an individual pixel of the screen to be rendered, this type of algorithm can be hard to parallelize because typically the raycasting can't be broken up into parallelizable steps. It typically looks like, "While not hit: traceAlongRay();" for each pixel, each frame. I.e. this algorithm can only trace one section of the ray at a time before tracing the next.

That raycasting algorithm is memory-latency-bound because it completes only when it finishes looking up enough memory locations that it detects the ray has intersected some 3D geometry. In other words, by reducing memory latency by 2x, and assuming memory bandwidth is sufficient, then this algorithm will complete twice as fast. This means instead of 24 frames per second, you might get 48 frames per second.

So, all that said, if it becomes common to have 1TB of regular RAM with the latency and bandwidth traditionally offered by GPUs, along with a surplus of available CPU cores to offload computations to, then software renderers will once again become preferable to GPU renderers. A software pipeline will always be more flexible and easier to maintain than a hardware pipeline, simply because the featureset of the software pipeline isn't restricted to the capabilities of the videocard hardware it's executing on. It's also easier to debug and maintain.

All of that means that it'll be easier for art pipelines to produce more complex, more immersive visual experiences than at present. But replacing the traditional GPU-based renderer with a CPU-based software renderer will only be practical if there's a major advance of RAM technology in the future, because current RAM tech can't match the memory bandwidth / latency of a modern GPU. Hence, any major developments in the area of volatile memory tech will be extremely interesting to graphics programmers.

In 1 TB of RAM you can keep without any compression 3d array 1000m * 1000m * 64m of voxels with 1 voxel being a cube 2 cm * 2 cm * 2 cm. And you can lookup it randomly with negligible latency and do real time raytracing on it.

If that won't change games I don't know what can.

Besides GPUs will obviously also use this technology if it really works.

If you're using integrated graphics there isn't any PCI bus involved. Even when graphics was off-die it was on the Southbridge.

And the bandwidth between the GPU and the GDDR on the graphics card doesn't have anything to do with the PCI bus either, except to a small extent when synchronizing with the CPU or initially loading textures or whatever.

Apart from the cutting-edge APUs (like AMD Kaveri implementing hUMA), the memory of integrated GPUs and previous generation APUs was separate and copying chunks of it in between happened via the bus.

Plus since we're talking about cutting-edge gaming, integrated graphics is irrelevant (and so are APUs).

"They've been expected to be on the market any day now for the past year or two."

The last I heard was second quarter 2014 by HP, that's been the release date for the last year or so. Supposedly they could release them now, but they are trying to time the market for business reasons.