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Comment by athrowaway3z | Hacker News Reader

I haven't really dug into the results yet, but my guess is that a SOTA model has been able to produce an accelerator that runs a model since around December.

The obvious next step is to get enough memory throughput to run that SOTA model itself so that it develop its own hardware.

But perhaps the more interesting question is this: Can an AI be given a big FPGA and design a model architecture that takes advantage of the fabric being reconfigurable.

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There doesn't exist a single FPGA that can fit an entire AI ASIC. You would need dozens stitched together, then comes the issue of clock speeds, FPGAs typically run far below reference. There also memory issues with FPGAs.

Companies typically combined multiple platforms together such as HAPs, Zebu, Palladium, fleets of FPGAs, and Virtual Platforms in order to design and verify ASICS. So, AI would need access to tens of millions of dollars of HW and Software in order to build and verify a chip design.

Tens of millions or billions? Either way that's not a blocker if it promises to pay off.

Tens of millions of dollars per AI agent isn't a blocker? In many orgs its hard for humans to get their hands on the proto equipment for long enough to run their tests.

> So, AI would need access to tens of millions of dollars of HW and Software in order to build and verify a chip design.

So, a seed round?

Yes a seed round is how much A0 tape out costs. The entire seed round. Let me know how you plan to pay for A1, A2, B0, etc and then the full production run (and then do it again in 6 months when the arch changes).

Startups usually think that they don’t need A1

I suspect an AI could design a purpose-built FPGA-like replacement that would be, for its purpose, significantly more effective than the current general-purpose FPGAs.

It could have a small improvement on power consumption, but the current design can already achieve 90% of the maximum theoretical speed of this hardware without giving up programability/flexibility

FPGA is not efficient in any way except producing very few pieces of a particular logic very quickly.

But I think the higher level logic could check out. If we can abstract the majority of the compute into dedicated ASIC then we might use something similar to FPGA glue to connect and reconfigure them to adapt to new model updates. A bit similar to LoRA layers that you find tune to adapt the model to your particular needs.

I assume that it starts making sense once you have big multi year contacts to run a particular model with only minor updates.

He is talking about a Coarse-Grained Reconfigurable Array.

Soon this will not be fiction anymore https://hex.ooo/library/last_question.html

this is really good. thanks for sharing

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