I did find it neat that it ends up actually reducing overall heat despite the multiple layer wafers as signals have less overall distance to travel as they move in layer space rather than across the chip.
I did find it neat that it ends up actually reducing overall heat despite the multiple layer wafers as signals have less overall distance to travel as they move in layer space rather than across the chip.
But my shoot from the hip thoughts are that this might end up being used more for mid range chips than high end. higher clock frequencies would probably compound the thermal laying beyond standard resistance and buffers.
Makes you wonder what is possible when applied this to much smaller node sizes. Interesting times ahead.
I mean, it is nice that they found out some properties (lower heat than expected), but you cannot patent that, I suppose.
Chips have been multiple layers since the beginning practically but it was also laid out in a somewhat 2D fashion of ALU here, FPU there, cache somewhere else, but now they are stacking functionality so that is isn't so discrete, in a 2D space it would get a little fuzzy.
It isn't mind blowing ground breaking stuff but it is very cool. Evolutionary not revolutionary.
Perhaps given the difficulty of acquiring and (using?) ASML machines, Huawei is looking for alternative routes to get there. Innovative nevertheless.