Nuvacore's unconventional CPU strategy – delay ISA selection as long as possible

One thing that will affect the design of their back end is memory semantics - if they want it to be more relaxed, as it is with ARM, or if they want to make sure reads and writes go out in order, as is defined by x86.

BTW, since someone mentioned x86S (the "legacy-free" x86 ISA) the other day, I wonder if it changes the memory write ordering requirement.

Related:

https://nuvacore.ai/