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  rseq_cs

   The rseq_cs field is a pointer to a struct rseq_cs. Is is NULL when no
   rseq assembly block critical section is active for the registered
   thread. Setting it to point to a critical section descriptor (struct
   rseq_cs) marks the beginning of the critical section.

I’m not sure I fully understand that man page (it never seems to say callers have to clear that field at the end of a critical section, for example), but doesn’t that mean the caller has to guarantee setting rseq_cs happens_before any code in the critical section? That’s a memory barrier.

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That is because you do not need to clear the field at the end of a critical section. It contains the contiguous instruction range where it fires so there is no problem with leaving it active forever unless you have another critical section where you want to use it.

No explicit memory barrier is required anywhere as the value is only read in supervisor mode and a privilege switch implicitly issues a LS-LS barrier on all major architectures. Even if you did not want to rely on that, you would only need a single S-LS barrier when you store the control structure the very first time.

> That is because you do not need to clear the field at the end of a critical section. It contains the contiguous instruction range where it fires so there is no problem with leaving it active forever unless you have another critical section where you want to use it.

Aha! So, to take advantage of that, a memory allocator uses the same abort handler for all operations?

TCMalloc has different abort handlers for each function: If preempted, we need to know where to restart.

If `rseq_cs` is no longer describing a relevant address, that is, the program counter has moved past it, the kernel just ignores it.

TCMalloc TL here :)

The code is executed by a single thread. Everything retires in program order. There is no need for a memory barrier between starting the critical section and its body.

It's just a compiler barrier (signal fence), not a memory barrier that concerns the CPU. The CPU is free to reorder loads and stores.

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