Can you design a chip: The protocol emulator ASIC competition

I may try this out. I pulled https://github.com/lawrie/fpga_pio, synthed the uart rx with vivado, and it was 1.4k luts, 322 FF. It seems within range of a starting point. I'm sure others have thought the same thing.

Interestingly some of the modules are deceptively simple. The only shift register was 475 luts to 38 flops. The entire thing is only maybe 6 significant lines of code, but it has multiple 64 bit runtime configurable shifts which means a lot of muxes. I've never asic'd before but hopefully a 2:1 mux is small.

Anyone who wants to collaborate? We can talk here, and otherwise my email is in my profile.