Reverse Engineering an ASIC
kjartanvandriel.github.io
kjartanvandriel.github.io
And I love the way that you solved it by understanding really well what each section does. I worked out bits and pieces of each one, but I realise now that I was missing a lot of clues that were right in front of me (for example that it represented an 11x11 grid, the operation of what I called 'the blob' on the lower right etc). And so far as I can tell you're the only one to find `TWO''NOT TOUCH`
Edit to ask: How did you find the `TWO''NOT TOUCH` output? I assume you worked it out via some structure? I gave up after 4 messages not realising it was possible to get more.
[0] https://ciechanow.ski/ - I particularly liked the one about the mechanical watch mechanisms, but honestly pick any
for the other output: 1) look at the inputs to the output block and simulate those, you'll get a condition you need to satisfy 2) check what those conditions mean by interpreting the other blocks 3) try to satisfy the conditions
Here's the source:
https://github.com/KjartanvanDriel/Kjartanvandriel.github.io...
The repo is actually a fork of a template repo for building a pages-based site:
https://news.ycombinator.com/item?id=49562657 - Solving the Jane Street reverse engineering challenge (4 days ago, 99 comments)
>"Deriving the netlist
Following these connections gives us a list of the gates and which pins share a wire. This is the
netlist.
For each gate, we keep its cell type so we know what it does, and for each of its pins, we record which wire it connects to.
One wire can connect to several gates, and we need to keep track of the particular pins it reaches. Connecting to a flip-flop's data input D means something quite different from connecting to its clock input CLK, even though both connections reach the same component.
With that information, we can
draw the circuit as a graph
. The components no longer need to sit where they were placed on the die. We can arrange them to make their connections easier to follow. We've also left the power lines out of this view, since we'll treat the supply as fixed when calculating the gates' logical behaviour."
While a netlist aka circuit graph (in a specific format, I might add) may seem like a very obvious thing to students of circuit design, I observed after reading this web page that they're sort of like:
the halfway point
between the chip design, the engineering, and all of the engineering ideas that transpired during that engineering, and the physical manifested silicon IC itself.
It's sort of like what an Intermediate Language (IL) is, between Source Code and a fully compiled Binary executable.
Or, sort of like what a blueprint is... between the mind of an Architect and a House.
Oh sure, one could argue that hardware generation source code written in a Hardware Description Language (HDL) occupies this level, and that wouldn't a wrong argument, but it seems to me that a netlist (more broadly a generic circuit graph) seems closer to this level, the halfway point.
Why is that important?
Well, in Engineering, if we can get to a netlist, we're halfway (or close to halfway) to our goal, of turning our ideas into silicon!
In reverse engineering (going the other direction!) if we can get to a netlist, we're halfway (or close to halfway) to our goal, of turning silicon back into the set of ideas (or an approximate equivalent) that produced that silicon!
So, the netlist seems to be the halfway point between ideas in the mind, and physically manifested silicon!
I never realized that, until reading the above article! (It doesn't state that explicitly, but you can kind of intuit it from the flow...)
Anyway, great article!