Gotham Silicon: 1μ CMOS process that will ship custom chips for –$100 in <24hrs
gothamsilicon.com
gothamsilicon.com
P.S. if you or anyone you know is good at MOS device fab and/or has extensive experience at the Berkeley Nano Lab I want to talk to you. Also if you want to make stuff with this kind of process let's talk.
These are available since about a decade, and would enable such short turnaround times for single chips.
Even an ancient 1 micron CMOS process requires something like one hundred process steps, many of which may need up to a few hours in an oven. If completely automatized, it could be done in a week for small batches, but not in a day.
One day could be achieved only for semi-custom integrated circuits, where the customer only specifies the interconnection of the components existing on the pre-processed chip.
Decades ago, when unlike today, there were a very great number of integrated circuit producers, there were many who offered a set of IC dies from which to choose one, where each variant could have different sizes, while including various mixtures of digital gates and analog components like amplifiers, comparators, voltage references etc., and after choosing one of the available base dies the customer would specify only how to interconnect the components and how to bond the die to the package pads.
With such semi-custom integrated circuits, it would be possible to complete their fabrication process in a day, by using direct exposure, instead of masks, for the final metal layers.
At the 1 micron level, the photoresist can be patterned directly with a laser projector. There is no need for an electron-beam machine, like for nanometer-resolution lithography.
That depends on the used substrate, they don't only have the ones which are in common use. They also don't need masks for anything, and their wafers are small. It's all a little hard to get, and the most current information is their Japanese site, with translation.
Have you looked deeper at theirs, or 'similar' stuff? I think it's misleading trying to extrapolate from an ancient process to this, 'or similar', because the roads taken by the mainstream(machinery and processing) do not necessarily apply to other roads, which others may have taken. And I don't mean by circumventing physics. Just applying them differently. For different volumes and scales.
To skip the use of masks, there exists only 2 possibilities.
For low resolutions, down to around the 1 micrometer claimed in the linked site, it is possible to use a small and low cost laser projector, which is also quite fast.
For higher resolutions, an electron-beam machine is needed, which works in a vacuum chamber, and which is big, expensive and slow (the slowness is not actually due to the electron beam, but to the fact that a chip that must be made with high resolution lithography would have many more components in the same area than a chip that can be made with low resolution lithography).
An electron-machine would be bigger by itself than what Yokogawa shows as being a "Minimal Fab", so I assume that Yokogawa uses a laser projector.
I could not find any statement about which is their best achievable resolution, but they give an example of a circuit made with 4 micrometer gate length, so I assume that their best resolution might be around 1 micrometer, which is compatible with a laser projector.
Yokogawa gives their processing time at one week, for a fabrication process with 98 steps, which is very close to what I have estimated in another posting here.
Actually, I think that the company whose site is linked in this thread might have just bought some equipment from Yokogawa, as that could match their claims.
Nonetheless, a one-day processing remains compatible only with semi-custom chips, where the customer just interconnects the pre-existing components, not with a fully custom chip.
Moreover, the Yokogawa equipment uses tiny wafers, where the maximum die size is limited to about 8 by 8 millimeters, and at that size you would get 1 die per wafer, with great chances that it may be a bad one, or if you make small 2 by 2 mm dies, you get just 16 per wafer, from which a dozen might be good, and so on.
So you must need only a small number of dies, otherwise the fabrication could take forever. Nonetheless, even such a small number of dies could be good enough for prototypes or for the needs of small businesses or individuals.
I certainly would like to order such integrated circuits, but for this the vendor would have first to publish the technical documentation with the characterization of the semiconductor devices that can be made with their fabrication process, to enable the customer to do simulations of their designs, before submitting one for fabrication.
A one-micron resolution is intermediate between that used for the Intel 80386 processors and Intel 80486 processors, but closer to the latter.
So it would certainly be good enough to make various custom circuits, which could substitute the standard microcontrollers or FPGAs together with any needed auxiliary ICs, where MCUs and FPGAs typically must include at least an order of magnitude more internal resources than are used in any single project, in order to enable their use in any of those projects, so a dedicated chip can be made much simpler and more energy-efficient.
I personally don't believe that even a $100 service delivering you 1 micron chips could compete against a $10 FPGA unless you are intentionally doing something the FPGA was not designed for like analog electronics or low static power.
Nonetheless, having actually worked as an analog IC designer, I can assure you that today, and especially when using a CMOS IC process, where the analog devices that are available, like MOSFETs, are inferior to the bipolar junction transistors and junction FETs, which were available in the fabrication processes traditionally used for analog ICs, it is completely impossible to make a competitive analog circuit that is purely analog.
Any CMOS analog circuit needs a digital part, even if it is something as simple as an amplifier, and more so for things like a power supply or a motor controller, or something that acquires data from analog sensors.
At the minimum, a digital automaton together with a lot of configuration switches is needed to perform the auto-calibration of the analog parts when the IC is powered on. Otherwise, things like differential amplifiers would be unbalanced, bias current sources and amplifier gains would have values very different from those needed for the circuits to work as designed, etc.
Digital parts may also implement in a simpler or more reliable way various kinds of control feedback loops and various protections to undesirable conditions, e.g. overcurrents, overvoltages etc.
So any useful custom CMOS circuit must be a mixed digital-analog design, i.e. it must include both a digital part, with flip-flops, digital gates and switches, and an analog part, with amplifiers, comparators, analog multiplexers, oscillators, voltage references, etc.
An one-micron CMOS process would be especially useful if its component list would include some NMOS transistors with a higher breakdown voltage, of at least 12 V, but preferably even of 20 V, or ideally of 25 V (to have a safety factor if using an 18 V power supply, as required by the gate drivers of some power MOSFETs).
An one-micron CMOS IC would likely use 3.3 V for the main power supply, and it should be able to use 5 V at least for I/O buffers. But if some transistors with a higher breakdown voltage would also be available, they could be used for open-drain output buffers that would be tied to an external higher voltage and they could be used to command directly some external power MOSFETs, without an intermediate gate driver. A standard 5 V I/O buffer could command directly an external GaN HEMT (gallium nitride switching transistor), but presumably the output current of the buffer would be low, so the switching of the external transistor would be slow in comparison with using an additional gate driver IC.
>I think it's misleading trying to extrapolate from an ancient process to this, 'or similar', because the roads taken by the mainstream(machinery and processing) do not necessarily apply to other roads, which others may have taken. And I don't mean by circumventing physics. Just applying them differently. For different volumes and scales.
this^ is my shtick. almost none of what i am doing is new or cutting edge. all just reconfiguration of existing tools/infra/techniques to do a different business model.
One day of processing would be possible only for semi-custom integrated circuits, like gate arrays, which have already been fabricated until a last step that only adds one or two custom metal layers to interconnect the existing components and then separates and packages the devices.
Even with that, one day of processing would be possible only for making a small number of chips, where the metal layers would be patterned without masks, by direct exposure of the photoresist with a laser projector. Making photolithography masks would take more than one day.
- Stock pre implanted wafers with oxide and polysilicon layers grown/deposited in advance to avoid any long furnace cycles at fabrication time.
-Use spin on dopant with rapid thermal anneal furnaces instead of sending wafer to external services for implant whenever possible
- Use SOI wafer and mesa isolation instead of more complicated and time intensive STI or LOCOS techniques
- SOI also gives you the ability to do work function engineering that could allow for junctionless devices, further minimizing need for implant/doping steps because you don't need to form wells in oppositely doped bulk silicon
- Instead of exclusively relying maskless lithography, which inherently means your exposures have to be done in sequence, you can instead rely on a combination of maskless and masked lithography so that as soon as you receive an order, you can start fabrication immediately by doing the first layer on a maskless setup while initiating mask writes for all subsequent layers in parallel across multiple mask writers. This parallelizes the lithography of every layer.
I am happy to talk more specifically if there is any feedback or questions about these points. AMA.
"This project is a collaboration with Miles Segal (Gotham Silicon), whose mission is to make microchip fabrication more broadly accessible. Creating ultra high resolution micron-scale imagery is the very first step in this process."
"Those are clips of Miles in the Columbia University Nano-fabrication Facility where he is developing a workflow to make the technology required to build microchips more accessible."
Another mention of the same: https://x.com/JoinEdgeCity/status/1966180823129878656
"Miles Segal is building an ASIC foundry by repurposing vintage nano-fab gear to deliver custom chips in 24–48 hours."
"During the week he was at @EdgeEsmeralda, he focused on making new connections – leaving with new energy, confidence, and momentum from countless serendipitous convos."
So it seems to be one very young dude passionate about revolutionizing semiconductor processing. Whether there is an actual market for a super fast turnaround at 1 um node, and whether he has the experience and the support to pull this off, is somewhat dubious.
But of course wonderful things do sometimes happen. While he was a student, Sam Zeloof became a legend by building a chip fabrication lab in his garage, using surplus and home-made equipment. Now he has a serious team, working on developing mini-fabs: https://fab2.com/ That looks pretty serious.
No, I don't see 3.1515 ;)
> custom chips for –$100
...are they going to make it up in volume?