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Comment by londons_explore | Hacker News Reader

RISC-V fragmentation bites again...

People bring this up to every RISC-V discussion but the same could be said for ARM or x86. For which ARM instruction set is built? Does this ARM cpu support integer division instructions, does support arm and thumb instruction encoding, only arm, only thumb, does it have a floating point unit, does it have neon, does it have MMU. Those are still relevant questions for ARM cores. On x86 situation is even crazier https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html . Some of the more recent CPUs list ~60 optional features. Even if you look just at generic common profiles you have i386, i486, i586, i686, x86-64, x86-64-v2, x86-64-v3, x86-64-v4. Just a single family of vector instructions has 6 different versions for example: SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2. I am not even going to try counting all the variations and optional instructions of AVX512.

On one hand this is an important topic, especially in contexts like which X86-64 profile are the software in Linux distro official repositories targeting.

At the same time no one is bothered by 20 cent ARM mcu not having instructions for atomic memory access, supervisor, SIMD or even floating point.

So if anything RISC-V instruction set optional feature sets are probably better structured and less fragmented (for now) than the current situation with ARM and x86.

For AP cores where Python actually runs it’s just “arm8” and pick your incremental version on top.

If you'd limit yourself to cores implementing the Application profile of ARM (Armv8-A etc), you'd do the same and limit yourself to cores implementing the Application profile of RISC-V (RVA23 etc). In that case, you can assume vector instructions and everything else.

If you don't, you get the exact same kind of question with ARM as with RISC-V. Do you use NEON or with SVE? Or do you conservatively compile without vector instructions at all even though it could possibly result in speed-ups for some loops?

For RISC-V that would functionally be RV64GC then. And you go incrementally from there as required.

Micropython runs on tons of stuff and while it isnt capital-P Python, its close enough for doing a wide variety of embedded work without learning a new language/libraries/etc.

I don't think you're giving ARM credit for the ever growing pile of features which are always optional or optional only on some versions of the ISA.

For example, can you use FEAT_CSSC to improve code size and performance? Well, if the target is <v8.7, the answer is no. If it's v8.7 or v8.8, well, then it depends on whether your specific implementation has it. Only after v8.9 is it mandatory.

Targeting armv8a is the moral equivalent of targeting RV64GC insofar as it will run on any application class core. Targeting that, however, leaves a fair bit of useful ISA enhancements on the table, and so you tend not to want to do that if you can get away with it.

The same problem exists for x86. Is $program built for x86-64 with SSE2? AVX2? AVX512? (I chose those three because they are programmer-visible. Programmers have to use intrinsics to exploit those ISA extensions effectively.)

For RISC-V the questions to ask are similar: Is this built for RVA20? Or RVA23? (The big feature of RVA23 is the Vector extension, again something that is programmer-visible)

Embedded RISC-V programmers will have to ask a lot more questions. But for most programmers the whole fragmentation thing is simply a giant meme repeated ad nauseam.

Intel has done such a good job keeping AVX512 support away from reaching ubiquitous adoption, it's insane. There are so many useful instructions in AVX512 which are just missing from AVX/AVX2 that you can't assume exist, even on modern CPUs, because Intel can't get their shit together.

The core problem was tying instructions to bit width. But I'm actually surprised that they didn't add AVX512 support through double pumped 256-bit operations like AMD did for a while.

> RISC-V fragmentation bites again...

Wrong.

What fragmentation? Find me a 64 bit RISC-V chip you want to run Python on that will not execute an RV64GC binary.

The issue is not fragmentation but ecosystem maturity. The exact same situation exists for all chips.

In most x86-64 Linux distros, CPython will be compiled to target x86-64v2. This means it will not use, for example, any of the latest vector math extensions that the x86-64v4 chip you are probably running is capable of.

The reason distros target the older profile is that not everybody has the latest hardware. There is no difference conceptually between x86-64 and RISC-V.

The difference with RISC-V is that RV64GC is more primitive than x86-64v2 and so it hurts more. And fewer people have RVA23 capable chips than have x86-64v4 chips. RVA23 is the RISC-V profile that describes essentially equivalent capabilities to x86-64v4.

But there is less RISC-V hardware in the wild in general. So, there is less legacy baggage to carry forward. RISC-V will go mainstream on a more modern profile than other chips.

Ubuntu 26.04 and newer require RVA23 support. And all new application class RISC-V processors will support RVA23. It will not be long before this is the standard RISC-V profile. It will probably happen before the x86-64 world standardizes on x86-64v4 (or even v3). So your “fragmentation” will be a bigger deal on x86-64 than on RISC-V.

But, today, projects like CPython are still using RV64GC level hardware. So, that is what they target.

Most of us do not have any desktop or server class RISC-V hardware. When we do, it will be capable of RVA23. And CPython will probably target that profile. Fragmentation has nothing to do with it.

Check back in 2 years.

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