AVX Bitwise ternary logic [VPTERNLOGD] instruction busted (2024)
arnaud-carre.github.io
arnaud-carre.github.io
See, VPTERNLOGD is a ternary bitwise instruction.
In theory, that means that it could (in theory, temporarily ignoring other factors like streaming, parallelism, memory access speed, etc.) replace the Matrix Multiply (aka "MatMul") component of LLM's, if, if and only if the weights in an LLM are changed to ternary (-1,0,1)...
Matrix Multiply is at the core of all GPU's and AI accelerators -- so alternatives to it, such as VPTERNLOGD (especially on older/cheaper hardware, as x86 AVX-512F apparently dates back to 2016), as well as Ternary LLM's -- may be worth a little investigation...
Yes, ternary LLM's do come with their own set of problems(!) -- but as a strictly-for-intellectual-curiosity x86 instruction, I think that VPTERNLOGD is pretty interesting...
Related:
"NativeTernary: A Self-Delimiting Binary Encoding with Unary Run-Length Hierarchy Markers for Ternary Neural Network Weights, Structured Data, and General Computing Infrastructure":
https://arxiv.org/pdf/2604.03336
VPTERNLOGD/VPTERNLOGQ — Bitwise Ternary Logic
https://www.felixcloutier.com/x86/vpternlogd:vpternlogq
Microsoft BitNet - Official inference framework for 1-bit LLMs
https://github.com/microsoft/bitnet
Ternary Mirror-symmetrical Arithmetic And Its Application To Digital Signal Processing by Alexey Stakhov (related: Nikolay Brousentsov, the "ternary principle" aka "Brousentsov's principles"):
https://computeroptics.ru/eng/KO/PDF/KO21/KO21334.pdf
DeepSilicon (YC S24):