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Comment by chasil | Hacker News Reader

How closely related is this CPU to SPARC?

https://en.wikipedia.org/wiki/AMD_Am29000

"Based on the seminal Berkeley RISC, the 29k added a number of significant improvements... One design element used in some of the Berkeley RISC-derived designs is the concept of register windows, a technique used to speed up procedure calls significantly."

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They're from roughly the same era (and the same as 68020s/396s/88ks/mips) - 29ks came out of AMD and sadly didn't fly as high as we hoped at the time - their unique stack management may have been part of that

I'd say the insane bus arrangements on released chips (unrelated to ISA itself) had more to say there - the 3 & 4 bus configurations only make sense if you're throwing a bunch of extra chips onto it to make a proper CPU module that will expose sensible single bus to the world. Instead you effectively got a harvard architecture design in way that is least helpful.

I think that has more to do with the amount you could get onto a die at that time, architecturally they had to move the MMU onboard first which left the cache(s) offboard

It's more that they implemented it for higher speed as the split bus meant instruction fetches didn't block data fetches and vice versa - but it meant that without glue logic you turned a von neumann architecture into half-broken harvard one (because there's no support for copying data between the buses).

Some of the models had normal bus that didn't require unusual things like dual ported memory controller or other weirdness.

Both are based on RISC-2 design, yes.

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