5 years ago I would have agreed with this but now I'm not so sure. We live in an era where you can tell a robot "Here's some C code. Design a 64-bit ISA, write the Verilog to implement it in an FPGA, write a C compiler for it, and use it to compile the C code I showed you earlier."
And now your ISA and your compiler are part of your moat. I can just see the VCs salivating.
There are thousands of people who could design such an ISA in a couple of weeks, without any AI assistance.
The hard part, which has always been the moat of RISC-V, is writing all the required support software for a new ISA, i.e. all the utilities from binutils (assembler, static linker, ELF/DWARF utilities), compiler backends at least for gcc and llvm, debugger (at least a port for gdb server), dynamic linker and standard C library, possibly some parts of the standard libraries for other programming languages.
Previously this could have taken years and it is the only reason that has always justified the choice of RISC-V for minimum cost, despite how bad the ISA is.
If today the porting of all these software support applications to a new ISA could be accelerated with AI assistance from a couple of years to a couple of months, that would certainly enable the design and use of custom ISAs, and RISC-V would lose its appeal.
With that said, RISC-V is a nice baseline for designing another architecture. Start with RISC-V, and go from there.
No links? You may have dreamt about it instead.
Let me know when you've got it all worked out and published. Should be easy, right?
That's why it's so bizarre that the RISC-V design is so awful.
The hard part is the software support side (though, as comments elsewhere in the thread point out, AI is pretty helpful there) and then those lovely pieces like specifying the precise behavior of interrupts.
If it had a snowball's chance in hell of going in to any kind of production anywhere, I'd have no problem spending the next month laying out an ISA. But, again, as this thread makes very, very clear: ISA really just doesn't matter.
Not bizarre.
The design is a direct result of the biases of its initial designers, and its original intended use-case. And TBH, if you assess it by its original design criteria, it's actually pretty good.
It's just by the time RISC-V had escaped containment and was starting to become a general purpose open ISA, it was a little too late to start from the beginning and consider what the correct design criteria should even be.
That feels like a "don't release yet" flag to me!
But I hear you.
The deliverable would be a (theoretically) complete specification PDF like RISC-V's.
I have little doubt that I or Adrian could do it, or plenty of others. It might not reach the quality of something like AArch64 with that level of resources, but it's not hard to beat RISC-V.
I'd guess low six figures for the beginning of that list and mid eight figures for the end. Real silicon also needs all the uncore stuff, which is easy if you don't care how it performs and very very hard if you do.
The only argument I've ever seen for RISC-V that's vaguely logical is that there's no licensing to Arm involved, but since I can get M0/M3 devices for a dollar or so with infinite tool and library support that's something that's totally irrelevant for most users. And if I don't mind going with Chinese suppliers there's no licensing to Arm being paid anyway.
Apart from being able to thumb your nose at Arm, I just can't see what the point of RISC-V is. Is that really all there is going for it?
How expensive is it to license the instruction set so you can expand it?
As an aside, Espressif (or Xtensa if you want to split hairs) have been quietly doing a lot of what RISC-V is supposed to do for years now. I know they've also been fiddling with RV32's but all the real work is LX6/LX7. They're best-known for their use in ESP32s but they also crop up in an awful lot of industrial/commercial gear.
Think it through. This is the HN comment section after all.
Even if you eventually figure out all the right questions to prompt, the experienced person is long done
If everyone can build a moat, there's just a lot of moats.
And how would you get this all into Clang? Nobody wants to use your custom compiler. It's certainly not going to be as fast as Clang!