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Comment by zephen | Hacker News Reader

> RISC-V is... fine

Exactly.

> It satisfies my two requirements for an ISA as a hobby CPU designer...

You probably have some unstated requirements as well, such as available toolchains and "vetted well enough to actually be able to run code."

Risc-V now occupies the Schelling point for people who, for whatever reason (rent-seeking and security top the list) want to leave the x86 and Arm ecosystems.

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Luke is too modest. Something in the region of 5 million chips containing his hobby CPU have shipped since launch on August 8, 2024.

Could you share a link or more details? What is this hobby CPU project?

Luke Wren works at Raspberry Pi and designed the Hazard3 CPU core that is in the RP2350 chip.

I think the GP is talking about the Hazard3 [1] core. This is one of the CPU cores besides the ARM M33 instantiated on the RP2350 µC [2]. See this article from Luke Wren (Wren6991) back when the RP2350 came out [3].

[1] https://github.com/Wren6991/Hazard3

[2] https://www.raspberrypi.com/products/rp2350/

[3] https://www.raspberrypi.com/news/risc-v-on-raspberry-pi-pico...

Thank you!

What I find interesting is that RP2350 is designed as "one or the other", no way to use ARM and RISC-V concurrently, and has fuses that can kill ARM M33 cores outright.

Makes me wonder if an "ARM cores fused off, RISC-V only, no ARM fees" SKU is possible.

Several of the peripherals in the RP2350 are also ARM IP.

You can choose Arm in one pair and RISC-V in the other pair if you want.

Are we talking about rp2350 ? Because the rp2350 can be config as pure arm soc.

In fact, if we are talking about successfull riscv soc, RISC-V esp32 may have better chance

They did explicitly specify:

> 1. Supported in mainline LLVM and GCC.

Which pretty well encapsulates the ecosystem requirements.

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