To make a 22 nF capacitor using a pair of copper pours separated by a 1.6 mm thick old school two-layer PCB, we would need something like 10 square feet! It would have to be an electronics art project, intended to be displayed on a gallery wall. :)
That goes down to something like 90 square inches if the separation is a 0.1mm thick layer of a thin four-layer PCB: still an impractically huge area.
Capacitors achieve their density in a small package by two tricks: extremely tiny dielectric gaps, and convoluted surface areas.
For instance, electrolytic caps achieve a big surface area due to using rough, anodized aluminum (or tantalum) for the anode (mnemonic: anodized aluminum -> anode). Then every ridge and crevice in that anode is available for capacitance due to using an electrolytic gel for the cathode. The roughness of the anode and the gel optimize for high surface area. Then the thinness of the oxide layer optimizes for a small gap size, also favoring high capacitance.
It is a special PCB laminate designed to create capacitance inside the PCB stack-up, typically between closely spaced power and ground planes.
Using siblings of this broadband capacitor (40 GHz, same package) in some designs. In assembly, those require decent process control. This 0201M package is closer to 01005 passives in pad size. Typically no solder paste is used, just flux. Solder mask alignment has to be very tight (thin web used as a dam only).
Cost per cap is reasonable where it is actually needed, other parts of the system are often orders of magnitude more expensive at those frequencies where performance matters. Where it gets the very high performance, is pillars/channels etched into silicon quite similar to how DRAM capacitors are made, just a “little bit bigger”. This allows for very low inductance and thus very high resonant frequency.
Ah, so reflow the solder on the package ends then? And I assume they have a fancy precision process for “tinning” the ends?