Nvidia’s Vera Whitepaper Has a Thread Loose | Hacker News Reader

Nvidia’s Vera Whitepaper Has a Thread Loose

chipsandcheese.com

208 pointspella46 comments

Ohhh look, value prediction. Exactly the kind of thing that led to Spectre. There will be a cottage industry of information leaks and mitigations for a decade.

I've been around now long enough I'm becoming more convinced that the tech industry in a nutshell is just relearning the same things on a 10-15 year cadence

Was it that long ago?

In today’s “agentic” world, everyone seems to have forgotten approximately everything we used to know about security. And this new CPU is going all in on value speculation. Delightful.

Maybe if “cyber” models get good enough at exploiting speculation attacks, people will start demanding equipment that is less prone to these attacks.

Attacker: I can run any code on this machine? Time for speculation attacks!

Attacker: Oh wait, I can run any code? I already own the machine...

Not really, Spectre showcased an attack from within a JavaScript sandbox, which isn't considered to own the machine.

Any side effects from speculation machinery can easily become a side-channel to infer values across security boundaries.

Did you forget about spectre and meltdown?

aarch64 has a CPU mode, DIT (Data Independent Timing), specifically for allowing software to request all fancy value prediction stuff to be disabled for the duration of processing of sensitive data.

(doesn't help when the attack target is general-purpose/user-controlled code leaking things, but if you're relying on a process not leaking memory plainly available to it without full careful control of what the process runs, you've already been fully-SOL on that for decades and nothing has nor will nor can change about that)

No way, ARM screwed this up less than Intel and at least allows user code to access the control bit. Intel’s equivalent, DOITM, is not accessible at CPL3.

I think security is going to get devalued in the near future. The safest strategy is going to be to need as little as possible of the stuff that you need to keep secret. And you won't keep that stuff on a device that is shared in any manner, or maybe even connected anywhere.

I don’t think picking a handful of SPEC benchmarks that approximate today’s most common agentic workloads (compiling code, interpreting Python) and then calling them “agentic benchmarks” is misleading at all.

That you need a whole lot of “ordinary” compute to benefit from the scaling properties of agents is the reason Nvidia is making this chip in the first place.

The four benchmarks selected are cppcheck, llvm, cpython, and gcc [1]. These are all essentially compiler benchmarks... and all of the compiler benchmarks in SPEC cpu2026! This makes the benchmark selection somewhat suspicious to me, since it's not particularly representative of a diverse set of workloads.

I also don't buy that it's a particularly representative set of tasks you might do with agents. Also included in the SPEC benchmarks are multimedia codecs, lossless data compression codecs, sqlite (i.e., database), all of which are going to be things you should easily throw into the sets of tasks an agentic workload might do. Cherry-picking just the compiler benchmarks instead of all of SPECint... again, it just raises a couple of eyebrows.

[1] To be honest, I'm kinda surprised that both gcc and llvm are in SPEC cpu2026.

The code in compilers is the closest to your typical app you can get in a benchmark like SPEC, eveerything else is actually far more specialized. Compiler code is full of small basic blocks, lots of branches, indirect memory access; it's actually harder to get good performance for such code, both for CPUs and compilers (that was part of the death of Itanium too).

That's true of most of the applications in SPECint (SPECfp is a different matter); there's nothing special about compilers there.

Where compiler code is going to get really unusual, I suspect, is that compilers tend to be a little mono-focused on relatively few data structures. I know I was able to get measurable (single-digit percent!) performance differences in LLVM making very small tweaks to layout in llvm::Value. By contrast, when I was working on Thunderbird, the only similarly small change I could think to make that kind of difference would be to "oops, all string functions are now a cross-DLL call" (and even then, only because string handling is so dominant in that kind of application). Another kind of difference is that the compiler-based benchmarks are going to be quite light in virtual or indirect function calls (there's more of an emphasis on switch-based dispatching than vtable-based dispatching in most compiler implementations), which is going to make it a poorer proxy for some kinds of applications.

Seconding this - having worked on LLVM and Firefox, the performance tuning of each application was very different. Even measuring the performance of an application like Firefox (in a meaningful way) is non-trivial, wheras compilers are much more approachable with traditional profilers (either tracing or sampling).

Death of Itanium was that it was a) VLIW and b) Intel was too arrogant. So it went to the same destination as later Larrabee and ATI/AMD attempts at VLIW GPUs.

That is, nowhere.

Also you are wrong and anyone sizing up an arch to put their loads onto must first try that load on it and not rely on "bah, compilers compile on it".

VLIW works for DSP applications, it's not an instant dead end. It's a good fit in cases where code path and memory accesses are predictable, like shader code.

Essentially every cell phone out there has a VLIW DSP like Qualcomm's Hexagon cores (though AFAIK Qualcomm is the only one who lets you run your on programs on their DSP).

Itanium only died because AMD exists, and due to various licensing reasons they were allowed to come up with AMD64.

In a hypothetical world where AMD wasn't allowed to do AMD64, and Intel stayed committed to Itanium: Itanium would still have sucked, and both PowerPC and SPARC would have out-sold Itanium by an even wider margin than they did in this reality. Itanium could only have succeeded if AMD64 wasn't possible and literally all of the competing 64-bit architectures were killed off by their owners so they could jump on the Itanium bandwagon. Itanium managed to kill off PA-RISC and Alpha and (high-end) MIPS roadmaps, but it still had competitors that were not just viable but actually more successful.

Except you would never had Windows running on either PowerPC and SPARC.

Remember, the very first Windows XP 64 bit release was on Itanium.

Windows NT on PowerPC was an actual product, although running in 32-bit mode.

Um...while not "OG Windows" I guess, PowerPC was an officially supported and shipping Windows NT 3.51 & 4 target[1]. It was released a couple of years before XP 64-bit for itanic. SPARC was a planned NT port, and while it never happened, it could have[2][3].

[1] https://archive.org/details/NT351PMZPPC

[2] https://www.techmonitor.ai/technology/undercurrent_bubbling_...

[3] Legend has it that the SPARC port existed, done by Intergraph, but for Reasons was never a product.

> Itanium would still have sucked

I'm not completely convinced of this.

If you ignore VLIW, you just have a very unexciting RISC ISA, but because of the VLIW, you get extra scheduling info that most RISC designs don't provide which might be advantageous. The real question is actually about the code density of 41-bit instructions and if it can be offset by the 128-bit package (and perhaps something like allowing new 24-bit compressed instructions).

Poulson already somewhat proved part of this as it added back a traditional frontend and even added some OoO capabilities and 4-way SMT. It wasn't earth-shattering, but it wasn't absolute garbage either.

The contemporaneous IBM POWER ISA was implemented in superscalar CPU cores with out-of-order execution and with SMT and it would provide superior performance in any equivalent fabrication technology.

The Itanium ISA actually had a few nice features, but it also had other bad features that outweighed the good features. Besides the static instruction scheduling in bundles, there was also the handicap of using SPARC style register windows, which slowed-down context switches.

The second version of HP PA-RISC, which was too quickly replaced by Itanium, would have had good chances of providing superior performance in comparison with Itanium, had it not been abandoned without a fight.

I mildly disagree - depending on your definition of "typical app". Most applications have much greater use of multi-processing and concurrent cross-thread (or cross-process) communication. Compilers, aside from high-level parallelism across modules, tend to be quite single-threaded applications.

If you're solely interested in single-core performance, then I would agree that they are a good stress test, but I think for a processor that is being sold on it's parallelism, they are not a great benchmark.

In the history of the SPEC benchmarks, the compiler benchmarks, like gcc, have been the best predictor of CPU performance for the applications that cannot benefit from array operations, so they cannot use the vector or matrix instruction set extensions.

The reason is that for the other benchmarks the CPU vendors have always succeeded sooner or later, to tweak their compilers and compiling options, or even the hardware of the CPUs, in order to get improved benchmark results that nonetheless are not indicative of the improvements in other applications.

On the other hand, the compiling benchmarks, like with gcc, and now also with clang, are too diverse in CPU resource usage and no special feature of the CPU has a significantly greater weight than others, so special tricks to enhance the benchmark results have never been found.

When looking at the past SPECint results, the values of the gcc benchmark remain the most reliable relative performance estimator.

I doubt that this will change in the near future.

Moreover, the multi-threaded compiling benchmark is also very useful, because it matches exactly a real-world workload that is extremely frequently encountered. Due to the great clock frequency difference between running a benchmark on a single thread and running it on all available threads, the single-threaded results have a very poor correlation with the multi-threaded results.

I think the choices of these workloads are deliberate, considering this is a large core count CPU linked to a FP-monster GPU with a high speed, low latency datalink.

The former implies per core memory bandwidth is probably not great, meaning SQLite wont perform as well, the latter meaning FP workloads are better done on the GPU, so video encoding wont be a high point. The idea is to run branchy integer workloads that fit into RAM imo, which is what these benchmarks measure.

Benchmarks are benchmarks. You can base your decisions on them, because good numbers on them will give you good numbers on other related things you do, but nobody who has been in this industry for more than a year will take a benchmark as a guarantee those same numbers for your own workloads.

Benchmarking is tricky. The only one that counts is your software running the way you run it. I often run a profiler while running unit/integration tests, but I know the results will not replicate actual use - it's just a proxy, because I don't want to profile everything in production unless the profiler has almost zero cost.

Let’s not forget the fact that despite their new market cap and being the beneficiary of having a near monopoly on making incredibly complex pickaxes during a gold rush… Nvidia is still the company with a long and consistent history of misleading their customers via marketing. Their greatest hits include:

- The digital equivalent of the VW emissions scandal where drivers detected when they were being benchmarked and altering rendering for better results

- Selling GPUs as having 4gb vram when it was only 3.5gb usable, the remaining 0.5 being absurdly slower and causing performance loss when used

- Using intentionally misleading naming schemes to obfuscate things like memory bus width being drastically different between what superficially appeared to be similarly spec’d cards

A dozen other less egregious but similarly disingenuous decisions

But to be clear, I’m a huge fan and continue to run Nvidia because their products are generally incredible regardless

You forgot their tensor core performance numbers "with sparsity".

That 4gb vram deal sounds ahead of its time. CPU caches are tiered, why not ram? Looking forward to future systems with 8gb ddr6 and 8gb ddr5. "Swapping to ram" would become a thing.

There are lots of platforms where RAM is tiered, and operating systems that support it. For example, CLX allows for a "NUMA node without CPU" abstraction; there was a HN article recently about Facebook cooking up their own silicon and Linux patches to implement this so they could expand DDR5 platforms with retired DDR4 memory. Not a new idea...20+ years ago I used mc68k & ns32k BSD systems that had a couple of meg of fast memory onboard and more, slower memory hung off a VMEBus. System tried to keep hot pages in fast memory and it worked reasonably well.

Xbox has that right now. Some memory channels have 1GB chips while some have 2GB chips. So part of your memory space uses all channels and part uses more like half.

That GPU was much worse though. If that .5GB had been moderately slower it wouldn't have gotten the same attention. But because it was a weird backup path to that segment of memory, on a design that normally runs all segments in parallel, it ran at 1/7 the speed of everything else. Overflowing into it was devastating.

AMDs marketing is just as sketchy. Their new Zen6 server page claims 3.3x performance per watt over vera on "agentic workloads" for a 100 kW rack. Maybe they are comparing a CPU heavy rack to an nvidia vera rack with 50 kW of GPUs sitting idle, who knows?

https://www.amd.com/en/products/processors/server/epyc/9006-...

> who knows?

You could try reading the footnotes, which include a link to https://www.amd.com/content/dam/amd/en/documents/solutions/a...

That doesn't clarify it and AMD says as much "Because these estimates rely on published results, internal measurements and projection-based scaling factors, they are intended to provide directional comparison rather than direct measured rack benchmarks."

It's marketing after all and nobody should make buying decisions based on that.

I'm glad to see the competition; nothing provokes meaningful change without it. Not surprised at Nvidia's blatant fabrications though; more of the same we've seen time and again (Superchip anyone, with 2+ year old designs).

This is neat. I'm only halfway through but some really cool discussion about the internals of the chips and what they offer.

I did appreciate the article and it's not AI slop by any means, but did anyone else notice how the language and grammar felt very LLM-written? Or at least edited from a LLM draft?

I used to really enjoy Chips and Cheese's writing, not sure if they made a change.

I haven't read any of their previous articles but I had to jump out and go through the comments here just because of how LLM-ist it felt. Right in first paragraph or two, it started feeling weird.

If you say it isn't just slop, I suppose I'll push past and read it. The topic itself did seem interesting.

So typical big corp marketing material disguised as whitepaper.

So, is this rip AMD

AMD announced a faster CPU two days later.

It’s a time-honored tradition to compare your upcoming product to the competition’s old news.

That said, looks like an impressive core and complete CPU built with it. Would love to see a smaller, affordable version.

Olympus’s raison d’être is to orchestrate GPUs—handling the control-heavy, latency-sensitive workloads that keep Rubin fed and the AI factory running without bottlenecks. Including tool calling and data marshaling.

They are not competing in the CPU space. Different markets.

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