Demystifying DRAM Read Disturbance: RowHammer and RowPress Phenomena
arxiv.org
arxiv.org
Regarding your linked comment:
> If we had properly tested and validated RAM, RowHammer wouldn't work, ever.
While it's exacerbated by physical defects and tight timings, it's really a fundamental problem with how DRAM works. It's frankly a miracle it works in the first place.
I don't think we can blame DRAM designers for flying a teensy bit too close to the sun here, since this is no problem in normal operation and only appears under adversarial scenarios. We can blame them for not fixing it once it was discovered. And we can definitely blame Intel for making ECC RAM a market segmentation feature.
Or refresh the whole thing after a certain number of row activations.
Or interleave activations with refreshes. Say, after every 5 activations, refresh the next row in the refresh cycle.
I'm not a DRAM expert. They can figure it out. I promise if you refresh the whole chip after every row activation you won't have rowhammer. It'll be too slow though. Somewhere in between is the fastest point where there isn't rowhammer.
How would you refresh the whole DRAM? Refresh is simply reading the row and writing it back, it is sequential in nature.
> Or interleave activations with refreshes. Say, after every 5 activations, refresh the next row in the refresh cycle.
It makes zero sense. Refresh is disturbance in itself. You are entering a recursion here where the mere act of refreshing increases the counter values of victim rows making refresh even more frequent. At the end you have DRAM that you cannot read from or write to at all because it’s always refreshes itself.
> I'm not a DRAM expert
Yes
Be so kind as to run the math on this for me? There must be something that I'm missing, because it looks like you're describing a system in which a refresh causes so much disturbance that another refresh is immediately required. Such a system seems incapable of reliably storing a byte and reading it back. The colloquial term for such a system is "unreliable garbage".
Well, if you need to refresh a bunch of rows after any other read, you will spend more time refreshing things rather doing useful work.
That's not how infinite sequences work.
If each refresh causes 1/n more refreshes, then your total time spend on extras is is 1/(n-1) of your original number.
So even if you had an extreme 5:1 ratio, 100 accesses would cause 20 additional accesses which would cause 4 additional accesses which would cause 1 additional access. It would be fine.
Just count accesses to each row, and refresh the adjacent row(s) when some limit is reached.
Same as a good car's computer doesn't make a bunch of rosy assumptions about whether the oil needs changing or not - the automotive engineers actually do their jobs, test the crap out of their engine designs, and base the oil-change criteria on the real-world test results.
(JIC: "Adjacent" has a range of meanings in English. Those go from "the singular closest neighbor, within further constraints on type, orientation, etc." to "relatively close to by some metric". But I am not an EE, let alone a chip architect, to know the "real insider" lingo here.)
Alternatively you would also count the refresh as a hammer on its adjacent rows.
Here's the actual Half-Double paper:
https://www.usenix.org/system/files/sec22-kogler-half-double...
Note two things:
- The entire chip is already refreshed every 32ms to 64ms, because the capacitors which implement DRAM lose their charges over time.
- The time required to induce an exploitable bit flip is (in one system tested) was ~22ms
So: Even if it was the whole chip - vs., say, the 6 nearest rows to the highly-accessed row - the more-frequent refreshes would not be a big deal.
> Alternatively you would also count the refresh ...
Sure. Or once any row access counter triggers a refresh, extend that to every row with a row access counter within (say) 25 of its limit. And if that ends up refreshing more than (say) 25% of the chip, then just refresh the entire chip.
I don't know if it's doable with the current ABI between the memory controller and the memory chips, without adding a bunch of expensive static memory to the controller. It may require a protocol change. Possibly just another wire to signal back to the controller that excessive charge leakage was detected and it needs to do an early full refresh, but even that means basically a new generation of RAM.
I'm thinking that either each memory chip gains a few bits per row to store predicted charge leakage (or an actual extra bit designed to leak faster than the main bits, coupled to a detector) or the memory controller would need an array of memory for the maximum supported number of rows. Either one is possible, but a design headache.
Why? Something like 70->90% of the world's DRAM is produced by three companies that are very friendly to each other. It makes no business sense to fix problems that you know your peer companies will not fix... that's spending money that you absolutely do not have to.
If the business/economic theory doesn't sway you, look way back to what happened to ISP speeds and pricing when Google Fiber so much as credibly threatened to start providing service in an area served by a mono/duo/triopoly. Or -more recently- how SpaceX demonstrated that the defense-contractor-owned space launch companies had spend decades wasting enormous amounts of taxpayer money by refusing to do any significant amount of research into bringing the cost to launch down substantially. ISPs and the space launch companies had no peers that would spend the resources required to provide a better and/or cheaper service to their customers, so it made absolutely no sense for any one of them to spend resources to break the truce and make them all far less money in the long run.
There are memory chips with a separate, limited, built-in self-refresh capability which is used during sleep mode to allow the controller to power down.
At some point in time, a few generations of DRAM ago, they have reduced the dimensions so much and without discovering adequate mitigations for the problems introduced by this, that the DRAM reliability has become inadequate.
The reason why they did this was to reduce the fabrication costs. It is likely that the pressure to reduce the fabrication costs has been caused more by the desire to increase the profit margins than by the intention to enable any price reductions, because even before the recent price increases there have been around 15 years with only negligible reductions in memory prices.
By increasing the fabrication costs, it would be easy to eliminate the RowHammer problem, while still having memory prices several times lower than the current prices.
However, the vendors do not want this. They want to find some kind of mitigation that would not cause any measurable increase in the fabrication costs. Until now they have failed to do this, but it is not clear how hard they have tried.
It is very likely that their failure to find anything that works has been caused in a good part by the secrecy that is typical for nowadays.
In the earlier times of the semiconductor industry, every manufacturing problem was described in public research papers, with complete details, and usually the right solution was found by someone else and then it spread quickly in all the industry, with much less concerns about "IP" than today.
Only this openness has allowed the creation of the successful semiconductor industry and of the "Silicon Valley".
But current prices you mean during this huge spike? Sure, you could double fabrication costs while dropping prices a lot from today's state. But that's not impressive. That still costs more than I want.
If you could reduce the price significantly from when it was sitting at $2-3 a GB, I'd be interested, but I'd need a bunch of evidence.
Intel decided long ago that you would need to pay more to not be subject to random bitflips. So it's an AMD system.
Replace your RAM or find what's causing this disturbance in the environment. Sooner or later you'll get a pattern the ECC won't be able to correct.
Ironically if you didn't have ECC you would instantly RMA such RAM as defective because even a simple memtest would quickly discover the problem, and "several bitflips in a day" would cause very obvious crashes all the time.
Something must be very wrong with OP's setup. Perhaps the RAM has been overclocked too far.
[1] DDR5's built-in ECC is not the same as traditional "end to end" ECC, and is meant to correct bitflips on the die, not between the RAM and the CPU, so ECC errors that you see are actually suggestive of a bad connection between the RAM and CPU.
Every system fails eventually.
ECC in DIMMs achieves this.
For myself, this has been the greatest advantage of always using ECC, that I have been warned early about the great increase in the frequency of errors in some DIMMs, after many years (over 5 years) of continuous usage, which has allowed me to replace the offending DIMMs and continue to use those systems for some more years.
It's very telling that when Rowhammer first appeared, authors of popular memory testing utilities added tests for it, and then quickly hid and disabled them by default because "too much RAM would test defective". I have no idea how they were convinced to do so.
When manufacturers are sufficiently lazy.
If you put a refresh counter into each memory row at like <1% overhead, you can actually guarantee that a thousand or a hundred accesses forces nearby cells to refresh and stay well inside their safety margin.