Schmitt Trigger: Robust Comparator Design with Hysteresis
wevolver.com
wevolver.com
This also means you'll want to ensure that any floating MCU pins are _not_ configured as digital inputs, as the Schmitt trigger circuit itself will waste power switching back and forth between high and low states constantly.
Stop right there. Floating CMOS inputs are generally not a good idea, even if they can be configured to shut off the digital receiver.
Yes, in some cases, you really can shut off the power to the digital receiver, but in the general case, you're better off configuring a pullup or pulldown on the pin, to keep it out of the CMOS transition region.
One way involves feedback connected to the input pin. This inherently lowers the impedance of the input and that alone makes it less susceptible to noise, even before you consider the altered comparison threshold.
The other way, such as in a 74HC14, involves a very high impedance input, but the threshold the input is compared to is internally modified. Modifying the threshold also makes it less susceptible to noise, but the impedance is so high that it still might have some susceptibility, especially if it's, e.g. routed to a connector pin that might not be populated.
Your statement:
> The entire point of Schmitt triggers is to not switch back and forth constantly without a good reason.
is essentially true, and some Schmitt triggers, such as those on many CPLDs and FPGAs, work by repurposing pull-up/pull-down circuitry, but not all of them work that way.
Schmitt triggers, in the general case, are circuits that cope with slow rise/fall times and a bit of noise on the input pins, rather than circuits that properly cope with completely undriven inputs.
In fact, FPGA-style low-impedance Schmitt trigger inputs can wreak havoc on things like the I2C protocol, because you might be effectively altering the undriven impedance and voltage of the bus, so you might want to put a discrete Schmitt trigger inverter in front of the FPGA in some cases, or, if you have enough pins, perhaps use a differential input on the FPGA and a couple of resistors and a separate output pin to set the threshold.
However, to me, this reads more like human stupidity than AI slop. Certainly, my AIs would do a better job. Rather, the nonsequitors and errors are similar to what I've seen from lazy undergrads filling space.
I have had the misfortune of seeing many similar papers before the rise of AI.
https://news.ycombinator.com/user?id=jay_wevolver
Is the account that used to heavily push this domain, I'm surprised it hasn't made it to the banlist.
However the general idea of using hysteresis for signal conditioning seems transferrable to other non physical control systems. I suspect that people who think about what the article is saying rather than reflexively declaring it to be slop could learn something useful.