SIMD for Collision
box2d.org
box2d.org
I did the first ragdoll physics system about 20 years ago, when we had less compute available.[1] GJK, which the author mentions, is the preferred algorithm for convex hull collisions. GJK is a hill-climber. You start with two points, one on each object, and walk them towards each other along edges, picking the direction that produces the most improvement. This is O(sqrt N) on the number of vertices per object.
That's with two random starting points. If you're doing this repeatedly, as in an animation, you can start from the winning points of the previous round. If the objects are not rotating and moving very fast, the recheck is constant time. If they move a little, it takes slightly longer, of course. Many modern programs don't use the incremental form, but it's much faster.
GJK is a very fussy algorithm numerically. The optimization involves subtracting large numbers and caring about small differences. Loss of significance due to underflow can be a problem, and can cause the termination condition to not terminate, with the optimization cycling between a few near-optimal solutions. The loss of significance problems show up as objects settle into parallel-face contact, which is why this algorithm tended to loop when put inside a physics simulation where objects settled. Passed tests with randomly oriented convex hulls all day.
This was hard to fix. I had a hack solution that detected cycling, and Prof. Stephen Cameron at Oxford finally fixed the numerical math to behave.[2]
(You can get his code from his web site, there's a substantial license fee for commercial use, and he died years ago. I licensed the code back in the 1990s, but can't sublicense or release it. If someone really wants it, they'll need to find his heirs and negotiate.)
You also need "good" convex hulls. Your options are hulls with polygonal faces that won't be perfectly flat due to numerical precision limits, or hulls with triangular faces that are sometimes coplanar. Using a convex hull generator which can enforce a minimum break angle of about 1 degree, with polygonal faces, seems to work best.
Now there's OpenGJK.[3] Haven't looked at that. Hopefully they've dealt with all these problems. I was doing this back in the stone age of game physics, when nothing worked out of the box.
[1] https://www.youtube.com/watch?v=5lHqEwk7YHs
- Collision using simple shapes is very optimized and fast
- GJK's complexity scales linearly with the complexity of the support function, while checking pairs scales quadratically, which is a big advantage of GJK
- GJK imposes a convexity requirement, so non-convex shapes need to be decomposed somehow, this is a non-trivial problem if your shapes are dynamically generated and you need to decompose them dynamically. An absolutely nontrivial problem.
- Physics engines have a 'broadphase' where they detect collision pairs using approximate shapes much more efficiently. For a fully general algorithm, this is needed for GJK as well, because of said decomposition. This gets rid of much of the quadratic behavior of simpler algorithms.
- GJK doesn't give you penetration distance which simple algorithms do - this needs additional work, but it might be tractable since that only happens after a collision was found
- A nice thing about GJK is that it generalizes easily to continuous collision detection
- In video games, developers can 'cheat' and design their objects to be easily represented by (composites of) simple shapes - cubes, cylinders, spheres etc.
So in all, GJK imo, is a 'mini-broadphase' and not separate technique (in that it forwards the actual query to the support function).
So if OBB-OBB collision is inherently 5x faster, and SIMD gives you another 6x speedup, you need 30 collision evaluations to break even. The nature of 2D vs 3D space is that crowding in 2D is much less feasible.
Generating good convex polygons is indeed a problem. I used QHull for that. QHull is overkill; it can generate convex hulls in N dimensions. But you can specify such things as minimum break angle, to avoid near-coplanar faces.
It would be interesting to look at some of the newer algorithms for approximate convex decomposition. These decompose a non-convex object into multiple convex hulls that can overlap slightly. Decomposing a non-convex object into multiple convex hulls perfectly tends to generate a lot of small parts you don't really need. Think about what happens at an elbow. I tried some academic code for that last year, but it wasn't very robust.
Simple shapes are not necessarily a win over convex hulls, because even a cube means testing 12 edges against 12 edges.
At one time I used a separating vector algorithm as a preprocessor for GJK, but the performance got worse.
> It would be interesting to look at some of the newer algorithms for approximate convex decomposition. These decompose a non-convex object into multiple convex hulls that can overlap slightly.
I wonder if you involve the broadphase in this, you could make an even cheaper decomposition - if you used something like BSP (which is a collision detection algo in of itself) that constrained nodes spatially, like BSPs, so if the convex decomposition nodes were to 'spill out' of the original model, those points would be rejected by the broadphase so they wouldn't matter.
Right now, most algorithms discard all the information built up by the broadphase.
In fact, if you listen to his recent podcast episode with Łukasz Ściga (which I linked in another comment), he mentions some properties that his current project (The Legend of California) relies on like determinism and reversibility. He also put up an earlier blog post with accompanying videos that show how Unreal’s built-in physics engine fails to resolve important collisions in their game correctly: https://box2d.org/posts/2026/06/announcing-box3d/
You then have the terrain chopped up into these 8x8s too, and can then do a collision test with at most 4 of them with the 1 character/entity mask.
Also, I see no mention of alignment in the post. I understand x86/AVX2 likes your load/stores to be aligned, even if it technically allows unaligned access.
So, for 32B loads/stores and 64B cachelines, it's 1.5x more L1 cache ops (as half of the ops will cross a cacheline); perhaps bad if you're L1-cache-throughput-bound, but less so if you're at L2+ as the extra work sits in L1.
Thus normally any CPU core that has a good SIMD throughput will also have a good throughput for transfers between the vector registers and the L1 cache memory.
The CPU cores of the last 3 decades that are considered well balanced can do the same number of FMA instructions per clock cycle (fused multiply-add) and vector register loads from the L1 cache memory. The throughput for stores is usually a half of that for loads, as that is typically enough.
For instance an AMD Zen 5 core in full configuration can do in every clock cycle two 512-bit FMA + two 512-bit loads + one 512-bit store (as a bonus, it can also do two 512-bit additions). A similar throughput is provided by the Intel P-cores used in their server CPUs.
If a CPU core would not have a memory load throughput proportional with the SIMD execution throughput, then much fewer programs would be able to reach a speed limited by the arithmetic operations, and most would be limited by the memory load throughput.
Even with the compromise currently chosen for designing CPU cores, the programs that use SIMD instructions are clearly divided into 2 classes, one where the performance is limited by the throughput of executing arithmetic operations and one where the performance is limited by the throughput of the load/store operations.
Looking at the Wikipedia article - I wonder if it is because SIMD and SIMT are enabled by hardware first
And you’re using languages like Python or Lua and not using a dependency that uses it for you, forget about it.
Simd is by far the most efficient cycles wise paradigm but its also brittle. When the shape of data is odd which is common enough you have to handle it properly which is sometimes a distraction from what people actually care about. Also GPUs exist, GPUs despite being way less power efficient are not brittle in this same way they have issues if memory is difficult but most problems work nicely on GPUs so people just do that because its easier and the tiering problem is less a big deal because GPU process instructions different than SIMD and batching and what not is left to hardware not the programmer
Intel didn't put SIMD in their chips speculatively; there was a lucrative market. HPC presumably. Maybe SIGINT.
There have always been SIMD accelerated libraries, but I assume that you're talking about more widespread hand-coded SIMD application code (either in assembly or using compiler intrinsics.) For audio DSP this caught on when SSE2 launched around 2000-2002[0]. All things being equal, the user being able to run twice as many of your plugin as your competitor's is a real commercial advantage (being super-slow compared to your competitors is also not a great look.)
Not all applications have such forces at play. For most of the intervening period computers were getting faster every generation anyway, so users were seeing performance improvements when they upgraded their hardware, with no developer effort. For me, adding features delivered more value to users than making the existing product run faster.
A few things that factored into my personal limited use of SIMD over that time frame (even though I did write some inline asm): overhead of maintaining compatibility with multiple CPU generations. i.e. AMD and Intel were not in lockstep (still aren't, see AVX512); my users' hardware was all over the shop ranging from latest and greatest to older than you would imagine; I wanted good OS backward compatibility; autovectorisation was supposed to be just around the corner (honestly it's not bad if you limit the compiler to a recent instruction set). All of this could have been addressed, but features were a higher priority.
In addition, that period was the era of "write once run everywhere." Portable code was desirable. Having inline asm was seen as dirty, using instructions that only ran on specific makes and models of CPU more so. SIMD was alien to the mainstream developer zeitgeist.
In recent years the calculus has changed: CPU clock speeds are stagnant, most if not all application processors have SIMD units. More people understand that most CPU compute is in the SIMD units. We seem to have reached a critical mass of open SIMD algorithm development in less niche domains (e.g. simdjson). But SIMD code is still not write-once-run-everywhere.
Modern, portable SIMD libraries are making it increasingly close to that. Highway is my personal favourite, thanks in part for its support for runtime dispatch.
(Disclaimer: I work at Google, but not on Highway, and am writing in my personal capacity.)
Unfortunately it was created before Unity could use vectorization and other C# engines were just starting out as well.
The source, a great resource for learning C# SIMD, even though its a few years old by now: https://github.com/bepu/bepuphysics2
It still can't unless you use Unity's Burst compiler. You're not going to be able to use bepuphysics2 in Unity because it was written for standard C#.
The official release and LTS versions are still some months out though.
On Apple CPUs, the original 64-bit FP instructions must be used when low latency is important and SME must be used when high throughput is important.
Most Android smartphones that were launched on the market since around the beginning of 2022 support SVE, so by the end of this year there will be 5 years of availability.
Of course there are people who have not updated their smartphones. I still use an ASUS Zenfone from 2019, which precedes SVE (though I think that this year I might finally buy a new smartphone among those that use Mediatek 9500 or Exynos 2600, because I am curious to experiment with the new Arm SME2 instruction set). Among the cheapest smartphones, there are still sold some with old Cortex-A78 cores (launched in 2020), which do not support SVE.
The 32-bit Arm architectures have used several kinds of floating-point units, with very distinct capabilities, so when compiling a program for 32-bit Arm CPUs you must always provide a specific FPU selecting option to the C/C++ compiler, the one correct for the target CPU, otherwise the performance will be suboptimal. (an example of how such a compiler option looks like: "-mfpu=fpv5-d16")
Only the 64-bit Aarch64 has cleaned up this mess, so for Armv8-A there is a well defined FPU instruction set, supported by all CPUs.
The Armv9.0-A and Armv9.2-A CPUs continue to support the original 64-bit FP instruction set, but they add SVE and SVE2.
The Armv9.3-A CPUs, launched last autumn, continue to support the original 64-bit FP instruction set + SVE + SVE2, but they add SME and SME2.
The Apple CPUs implement the original 64-bit FP instruction set but they do not implement SVE/SVE2 (except in a non-performant "streaming" mode), but in the past they had a non-documented AMX extension and now they have SME.