Charting RISC-V's Future in HPC

hpcwire.com

10 points·rbanffy··7 comments

Hard to have vendor lock-in without vendors! Not that I think anyone should be lining up to produce what appear to be clones of the Intel Xeon Phi.

Funny thing: modern Xeons are getting closer and closer to the core and thread counts of the Xeon Phis. A 6980P has 128 cores and 256 threads, with AVX-512 and AMX.

It always made more sense as the host CPU; the Knights Landing product was vastly more useful. The problem has always been hanging your compute on the far end of a PCI bus. In AI when you're just shipping FP16 around it doesn't matter as much, but in the HPC world we want FP64, and I/O constraints kill this product dead.

The optimal case was always loading up the coprocessor memory and letting it crunch the data until it finishes. One nice thing was the low cognitive load at a time CUDA was not a great experience - it just pretended to be a normal computer, if a bit memory-starved. A classic “lopsided machine”, good for some things, not great for most others.

And I agree - it was getting a lot better by the time it was killed. I’d love to find a reasonably priced Phi machine, but it seems the latest batches, with proper virtualisation support, went straight into supercomputers.

RISC-V is inevitable.

RISC-V is rapidly growing the strongest ecosystem.

Jim Keller: "RISC-V is the Future"

I liked it better when PowerPC was the future.

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