Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm | Hacker News Reader

Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm

semiconductor.samsung.com

127 pointsits_ajseven46 comments

https://en.wikipedia.org/wiki/Field-effect_transistor

> By stacking multiple nanosheet channels, the effective channel width can be maintained even within a highly compact footprint.

The fact that this level of precision can be achieved on 300mm wafers over many dozens of separate steps in separate devices is an insane achievement on its own.

A much greater achievement than training frontier models, or building any kind of software stack, if you ask me.

Yet everybody seems to think the moat is with the AI companies or nvidia.

Now that it's been clear there's money to be made for a little while, inference engines will be commoditized the same way as bitcoin miners.

For sure but a weird comparision. These are completly different technologies.

I don't think a optics engineere can train a frontier model.

But also a frontier model requires a lot of compute.

And the money we are paying for it as consumer is ridiculously low. And yet all we have ever heard was they are being ripped off.

Generally speaking both HN and the internet rarely appreciate hardware advancement.

How about heat? Seems these days it's the heat above everything else that's the issue. And more density would only aggravate it.

What you loose in heat you gain in speed caused by proximity. Perhaps this will allow for lower voltage and thus less heat.

Except hot spots quickly reach the melting point of silicon these days. That creates, let's say, a rather steep drop off in performance.

Pure silicon melts at 1400 C

You must be thinking of something else

In NAND, data loss is proportional to temperature. I don’t recall how logic circuit errors behave.

I take your point, but an IC is not pure silicon

Indeed. For instance, dopants can diffuse and metals can intermix with silicon (silicide formation), both degrade device performance. Solder and packages melt before any of this happens.

It is easy to melt the semiconductor in a semiconductor device long before the solder or package materials are melted.

Above a certain temperature threshold, the electrical resistance of semiconductors drops exponentially with temperature, which is why NTC (negative thermal coefficient) thermistors are made of semiconductor materials.

This causes a positive feedback loop that increases the current very quickly and concentrates it through a narrow channel through the semiconductor (so the current density can be extremely high even when the total current is still low), which can easily reach 1500 Celsius degrees, melting the silicon, while the temperature of the package and of the solder remains very low (because the time is too short for the temperature to propagate outwards from the melted silicon channel).

Nope, thermodynamics is weird at small scales. Hot spots can absolutely reach 1400C if not designed not to. Sophie Wilson (initial architect of the ARM processor) has talked about how poorly designed silicon can reach point temperatures hotter than a nuclear reactor steady state.

That’s crazy. I thought maybe some of the other elements used in modern semiconductors might melt first. The wiring seems like a potential problem. But before that even the elements they use in the transistors themselves could be an issue.

The wiring has lower resistance for a bunch of different reasons, so the heat has a tendency to be concentrated on the transistors themselves (which are mostly silicon, just doped).

Like I have already said in another comment, semiconductors and metals behave differently when temperature increases.

For metals the electrical resistance increases with temperature, causing a negative feedback that limits the increase of the temperature, while for semiconductors the electrical resistance decreases with temperature above a certain threshold, so once that threshold is reached positive feedback increases the temperature very quickly until the semiconductor is melted, unless there is some protection system that limits the power dissipation through the semiconductor.

That is why it is very easy to melt silicon in an integrated circuit or in a discrete device, despite its high melting point.

Very surprising! Thanks for sharing

The melting of silicon was a common phenomenon already during the second breakdown of power transistors, e.g. in audio amplifiers or in TV sets, more than a half of century ago.

In semiconductors there is a positive feedback between temperature and the current that passes through them, so once a certain threshold is passed, the current and the temperature grow very quickly until the semiconductor is melted. This is opposite to the behavior of metals, where resistance grows with temperature, tending to limit the current that passes through the metal, when it overheats.

The currents through the transistors of SOTA logic gates are very small, but their volumes are also very small, so the power density is similar to that in high power transistors.

Thus thermal breakdown that leads to silicon melting is easily achievable. This is why any modern CPU has on-die temperature sensors, so that temperature is monitored and power dissipation is limited, to ensure that the threshold that triggers positive thermal feedback is never reached.

wow, i had heard of transistor thermal runaway, but i didn't know you could reach silicon melting point temperatures. though i guess in hindsight it makes sense that, considering that during the manufacturing process semiconductors are already exposed to very high temperatures, if you are instantly permanently altering a device with heat (as you do when you destroy it through thermal runaway), you must be reaching comparably high temperatures.

what type of people look at heat transfer at the device level in an IC (and at such short time scales)? where can i learn more about that? this looks like it could have an impact in analog power circuits, because even if you don't destroy the transistor you could alter its characteristics, but i haven't seen a lot of attention being paid to that. personally i guess i figured individual transistors never went significantly beyond the temperature ranges we already consider for the circuit as a whole.

thank you for sharing

I wonder if the proposed CPU/GPU laser cooling technique that was on here a few days ago would penetrate the Si layers?

https://news.ycombinator.com/item?id=48510375

The future is to replace the Si base with something else. Silicon Carbide has higher thermal conductivity. Bismuth-based composites provide much higher frequency.

https://semiengineering.com/the-race-to-replace-silicon/

https://www.plantengineering.com/semiconductor-material-that...

Not an expert but I wondered this too and did some searching. My understanding is the laser cooling isn't expected to be applicable to silicon logic anytime soon. Its applications are more for specialized contexts like cooling quantum sensors, resonators, imagers, etc.

The big barrier remains heat and this 3D stacking (aka CFET) makes heat worse by increasing density. It's possible much of the density gains offered by CFETs will remain unutilized unless other approaches to solve the fundamental heat problem are found, possibly discovering new high-conductivity MDI materials.

That's always an issue, but the industry seems to be moving away from 2D circuits.

Reducing trace length seems to be the way forward for faster/larger circuits. Signal propagation time on-die is becoming an issue.

Things like Huawei's Logic folding, or TSVs, and so on, attack the issue by reducing signal travel time.

This looks like another building block in that direction.

There's also some push at cooling chips from both sides.

If heat is produced by conductors resistance then shorter paths would lead to less heat produced.

I'm not certain (never did hardware), but I thought the transistor switching cost was one of the bigger sources of energy loss, not internal conductor resistance between transistors?

Makes sense, I also doubt that they haven't minimized resistance to minimum already.

You're correct. Dynamic power consumption depends heavily on frequency, but it's definitely more of a limiting factor than static power consumption which as I understand it (I'm also not an expert) is mainly important for things like low power microcontrollers.

The shorter connections could lead to faster rise times though, right? I.e. less capacitance or inductance interfering with getting the field gate charged up?

And the main loss with switching transistors is in the intermediate switching states where it has less than its "full" resistance.

> The shorter connections could lead to faster rise times though, right?

Not if you replace that length with more capacitors stacked on top of each other.

Hah, yeah.

I've been naively assuming they are now making high quality vias, so that circuit characteristics would be similar in either vertical or horizontal direction.

Heat is mostly driven by leakage current and gate capacitance.

The big issue today is leakage currents. They typical account for around 30%-50% of total chip thermal budget, and they get increasingly difficult to control with smaller devices and lower voltages. They're also get worse with increased temperature(!).

The stacked devices here aren't the worst for leakage currents, but they're not fantastic either. Look at the 2nd graph in section 5: You'll see that the current never drops to zero over the range of gate-source voltages (for V_DS=0.7V). The minimum point is the best-case leakage current, and you can see it's well above zero! (The units on the vertical axis of the graph are unknown btw: The label reads as "current drain-source, arbitrary units")

> A city provides a useful analogy. When available land becomes scarce, urban planners initially reduce the spacing between buildings and use roads and open spaces more efficiently. Eventually, however, further horizontal expansion becomes impractical. At that point, the solution is to build upward. High-rise buildings create more usable space on the same piece of land by utilizing the vertical dimension.

Really? someone tell that to my city

It only works for cities designed from the ground up for such density, simply because of all the supporting infrastructure that humans need (utilities, roads, public transport, education, entertainment, recreation).

Retrofits are insanely expensive and often fraught with issues.

This seems like it could accelerate the transition to sub-1nm nodes (previously projected to mid 2030s), maybe by the end of this decade.

Why does it seem like that?

so whats the implication for average joes here ? have no idea what these technical terms mean....

Computer chips go faster

Making chips smaller is very hard at the nanometer sizes, and it requires the kind of expert equipment made by one single Dutch company (ASML) and expertise only the likes of Taiwan's TSMC have.

Stacking means keeping the same size, but adding more of it so it matches the same compute power as the more advanced smaller chip designs.

China (who is banned from buying from ASML) is currently pursuing stacking as a short to medium term strategy until they can catch up to TSMC.

https://policy.economy.ac/news/2025/11/202511284344

excellent answer thank you that makes a lot of sense are there any downsides to that ? more heat ?

FET: https://en.wikipedia.org/wiki/Field-effect_transistor

Thanks! we'll put that in the toptext too.

Permanent and global boycott of Samsung due to them shoving ads into smart refrigerators.

They’ll keep pushing till you push back.

Just don't buy smart refrigerators. They make other very good products.

Good luck with that

Basically every smart fridge they make has an equivalent (nearly identical) non-smart variant. You don't need a smart fridge, you don't need a screen on a fridge at all.

As an aside, my old Westinghouse fridge shows me ads. The ads arrive in my mailbox and then I put them on the fridge with a magnet. One of the ads on my fridge at the moment is for Dominos.

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