How does wired internet technically work on these chips? Is it just 8 dedicated GPIO pins?
A few SoCs provide integrated PHY transceivers, but usually it's an external chip.
[1]: https://www.ti.com/lit/ds/symlink/dp83867e.pdf
[2]: https://yageogroup.com/content/datasheet/asset/file/DATASHEE...
Usually have to do this for any interface when the signals don't come in right at logic level, like CAN, RS-485...
although it's not always exactly 'just' logic level conversion.