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Comment by tverbeure | Hacker News Reader

> dubious applications of AI

Leaving aside the ethical aspects of using AI (not because they're not valid, because they're off topic for this discussion), in my line of work, the capabilities and productivity improvement of AI are staggering. Most of it is not writing the new code, which is but a small part of chip design, but everything else.

I can't give a concrete work example, but here is an experiment that I ran a month ago. https://tomverbeure.github.io/2026/04/12/AMIQ-License-Key-Ge.... If it can do that, it's not hard to imaging similar use cases related to root causing complex simulation failures. It is frighteningly good at that.

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> use cases related to root causing complex simulation failures.

That's a pretty interesting use case. I assume this is for RTL simulation given the thread, but how do you connect the output of the simulator to the AI?

For a small case, a colleague took a screenshot of waves in the waveform viewer and pasted it into the AI tool. It worked.

But for large cases, use tools to extract all interfaces from the waveform file and save it as a text file, or add $display statements in the Verilog itself to dump the transactions. A SOTA LLM will eat it up. You point it to the RTL, a log file with hundreds of thousands of lines, and give it a few lines to explain how it is supposed to behave. Just tell it "My simulation is hanging. Figure why." Wait 15 minutes and it will tell you why it hangs and which line to change in your code to fix it.

I've done the experiment after the fact: I had spent ~3 days to fix complicated 3 bugs. I then rolled back the code and told it "Here is the spec. Find all the bugs in this code". It found all 3 bugs in around 30 min. That's when I realized that things won't be the same anymore. (And don't get me wrong: I love debugging simulations.)

SOTA = State of the Art? Like say Claude Opus 4.5? I actually want to try this out.

I think I used Opus 4.6 1M.

Thanks! I'm going to give this a shot on a nasty simulation I'm presently working on... :)

This is why I asked:

>And why not take the alternative approach of identifying the subset of people who have indeed found solid uses and spread their best practices around?

A bottom-up approach has a far better chance of finding those particularly good use cases, and if you lean on the people how found those fits, they're more persuasive than top-down edicts. They actually know what they're talking about. If the point is to leverage AI for better work outcomes, someone with your experience is far more valuable than "here's a dashboard, make the number go up," which seems to be what's going on at Amazon.

How do you know up front who will find the best use cases? Both approaches can work.

I'd bet my life savings that the person who is forced to use a tool by top-down edict is less likely to find a valuable use case than the person who is sincerely curious about said tool.

Your mistake is thinking that all people who don't use it are doing so because they're not curious about it.

Have you tried to change your HDL to something more modern like Bluespec System Verilog or, god forbid, anything embedded into Haskell or Scala?

I read that BSV source code is about three times shorter than similar design in Verilog and also has three times smaller defect density (defects per significant line of code). So just by changing the HDL from Verilog to BSV one can have nine (9) times less defects in the design.

BSV won't help for cases you didn't think about a corner case. (I use SpinalHDL/Scala for all my hobby projects, BTW, and yes, I tend to make less mistakes.)

Fair points! Thanks for sharing the write-up as well - great read.

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