Loop inductance is what really matters with decoupling. Once you understand that, it becomes really easy to make good decisions. This article explains how you can approximate the inductance for a given layout, so it makes evaluating layouts much simpler. It actually used the data from the paper you referenced in example 3!
https://learnemc.com/estimating-connection-inductance
You can even use mutual inductance of vias improve performance, either by having vias spaced close together and in the right order (https://learnemc.com/decoupling-for-boards-with-widely-space...), or arranging capacitors in alternating or doublet layouts (https://incompliancemag.com/decoupling-capacitor-design-on-p...).
As you say, just having power planes and directly connecting to them is almost always going to be superior to using a trace, despite seeing this all the time, especially in datasheet example layouts. It made sense for 2 layer boards, but not today. Just think, the inductance of the planes is practically zero, and distance to the plane from the components is going to be on the order of 0.2mm, round trip 0.4mm. Is there any way I could place the capacitor 0.4mm away from the pins to achieve an equivalent inductance? And even if you could, you can't add extra vias to lower inductance, and you don't benefit from mutual inductance.