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Comment by lynguist | Hacker News Reader
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lynguist
·
Indeed!!
MIPS - $zero
RISC-V - x0
SPARC - %g0
ARM64 - XZR
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classichasclass
·
PowerPC: "r0 occasionally" (with certain instructions like addi, though this might be better considered an edge case of encoding)
Findecanor
·
On 64-bit ARM, the same register number is XZR in some instructions and the stack pointer in others.
matja
·
Alpha: r31, f31
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