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Comment by Joel_Mckay | Hacker News Reader

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Joel_Mckay·

> realtime computing

Even with HDL defined accelerators, that statement may not mean what people assume. =3

https://en.wikipedia.org/wiki/Latency_(engineering)

https://en.wikipedia.org/wiki/Clock_domain_crossing

https://en.wikipedia.org/wiki/Metastability_(electronics)

https://en.wikipedia.org/wiki/The_Power_of_10:_Rules_for_Dev...

https://www.youtube.com/watch?v=G2y8Sx4B2Sk

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I'm talking almost exactly about this haha. Flight software representation!! Although I have no experience programming FPGAs, I hope to gain some soon. They seem like the ultimate solution to my IO woes.

A bit legacy these days, but I liked the old Zynq 7020 dual core ARM with reasonable LUT counts.

https://www.youtube.com/watch?v=FujoiUMhRdQ

https://github.com/Spyros-2501/Z-turn-Board-V2-Diary

https://www.youtube.com/@TheDevelopmentChannel/playlists

https://myirtech.com/list.asp?id=708

The Debian Linux example includes how to interface hardware ports.

Almost always better to go with a simpler mcu if one can get away with it. Best of luck =3

No way, was looking at the Z-7045 for a work project literally today. And yep I agree, simpler solutions have simpler problems lol. Thanks for the recommendation, I'll give it a look!

That chip was hitting a sweet spot in terms of DRAM controller and distributing memory bandwidth between CPU cores and fabric. Xilinx was very afraid of screwing this up and running into bottlenecks. One of the best balanced chips in that regard with a great controller. Your best bet still was to keep everything in blockram as much as possible and only read and write DRAM once at every end of the computation...

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