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Should say DRAM, SRAM does not have this.

Indeed. And only for certain DRAM refresh strategies. I mean, it's at least conceivable that a memory management system responsible for the refresh notices that a given memory location is requested by the cache and then fills the cache during the refresh (which afaiu reads the memory) or -- simpler to implement perhaps -- delays the refresh by a μs allowing the cache-fill to race ahead.

(seems that in the earlier submission, https://news.ycombinator.com/item?id=47680023, jeffbee hinted that IBM zEnterprise is doing something to that effect)

Said that, I'm not convinced that this is a big issue in practice. If you really care about performance, you got to avoid cache misses.

None of the DDR2 and onwards memories have anywhere near enough bandwidth to meet refresh frequency on each bit by you even just reading it in a loop.

The refresh that we do is run in parallel on the memory arrays inside the RAM chips completely bypassing any of the related IO machinery.

And those memory arrays cannot detect access from the bus?

I'm not saying that it's easy or cheap or worthwhile (I'd rather guess it's not in most cases), but I don't see why it couldn't be done.

Ok I've consed a D onto the title above.

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