Nice specs! Looking forward to seeing how this and the other projects on Waferspace goes. Being able to produce 1k chips at a reasonable price will hopefully do wonders for open hardware / open silicon.
If you want to make better chips, like the low power Apple Silicon for example, you create your own EDA software tools to make the innovation. Creating a new transistor like the CFET [1] means writing new physics simulation tools, for example.
The outdated 1990's and buggy Open Lane software for example limits what kind of RAM transistors you can make or the complexity of your design.
My team makes asynchronous chips, free space optics photonics, ultra dense 2 transistor SRAM, niobium SQF chips, wafer scale integrations. All require bespoke software simulation tools, netlist rewriting tools, cross-reticle stepper exposure software (a software change in a $400 million dollar machine), etc etc. Making hardware near atomic size structures is mostly a software job. Hardware is software crystalized early, Alan Kay quips.
[1] https://www.imec-int.com/en/articles/imec-puts-complementary...
On these multi party shuttle projects this gets simplified into a price list where they quote you a high ball-park number that covers your test chips cost by a wide margin. The actual cost is never disclosed, certainly not on price lists.
A mask set maker and a chip fab create half of your product, they own that intellectual product and they won't even tell you what it has cost them. They merge their product with yours, now thyey co-own your product. There are only a few competing companies world wide (and getting fewer every year) and they compete on all this non-disclosed stuff. Prices above all. Never belief what you read on the internet, especially in the chips war industry.
[1] https://www.google.com/search?client=safari&rls=en&q=shuttle...