Second Revision of 6502 Laptop | Hacker News Reader

Second Revision of 6502 Laptop

codeberg.org

115 pointsuticus24 comments

I was writing algorithms to find prime numbers on a 6502 some 31-32 years ago and I hold dear memories.

There have been multiple initiatives to remake a 6502-based computer. My today's self does not appreciate the 8-bit limitations however; artificial and not limiting in the way that sparks creativity. I'd much rather work with a 32-bit micro PC (I believe they're called micro-controllers?) and be able to address more memory and then try to minimize its use, rather than being stuck at 8/16-bit addressing forever.

But every time I see a 6502 post, I get a tinge of longing. :)

What is the GPU? Some sort of FPGA?

Edit: Also picture missing from the page, the keyboard:

https://codeberg.org/TechPaula/LT6502b/src/branch/main/Image...

Edit2: Found a few suspects in BOM: ATF1508AS-7AX100, ATmega88PA-AU, ATmega644P-20A

Would love to know what each will do!?

The previous one hints a bit: https://codeberg.org/TechPaula/LT6502

A blog entry: https://www.maddox.pro/?p=414

Imagine in steampunk fashion wed get an alternative future timeline where computer tech froze in 80s due to some physical limitation that prohibited shrinking transistors. all typical laptops would have same config as this awesome project. what would the society become?

Laptops would be a lot less common. If computers were stuck in this era for that long, fewer people would be interested. Prices would be high.

I believe the actual silicon of a 6502 is much smaller than the DIP package, so even if we couldn't shrink the silicon itself much more, you could just take up more space inside the package, and use a package that has more pins in it, like current CPU designs. You would probably hit a bottleneck at some point since I believe the speed of light is a problem for processing speed at some point, but then I'd expect we'd just go into massively parallel systems, with multiple cores acting somewhat individually

Okay what if something else had prevented something better than a 6502 being mass market available?

the 6502 package would probably shrink to use something like a BGA package, and you could probably make some kind of "multicore" system using 6502 processors. I'm not knowledgeable enough to say how feasible that would be, but you could probably use something with shared memory regions to pass data between them and run code in parallel.

If you are absolutely limited to 6502 DIP chips, there would probably be more prevalence of large mainframe systems and single 6502-based "terminals"/"thin clients". The mainframes could use systems similar to the Transputer or the Connection Machine to use large amounts of (comparatively) low-power processors to make a single, more powerful computer. They both used custom processors, with the Connection Machine in the early 80s and the Transputer in the late 70s. You could probably reasonably easily create a "graphics card" style system, comprised of many 6502 cores in a SIMD configuration.

I don't know how easy it would be to implement wifi or ethernet with only 6502 chips, so communications with the mainframe might be quite slow

I was thinking lately about how much memory you could handle on a 6502. The BBC Micro had a 16KB block of RAM paged between up to 16 ROMs/RAM but if you could have 256 banks you could do 4MB. One problem is that that would require a very large PCB. Another problem is that the OS searches for commands on all the ROMs and this would become slow for so many banks; one solution would be to limit the ROMs to the first few banks and let the rest be RAM.

It could be useful for some sort of minicomputer for business applications.

Depends entirely on what banking scheme you use. Nothing stops you from adding e.g. an 8-bit banking register (even two of them, one for instruction fetches, another one for normal memory reads/writes) to serve as bits 23–16 for the 24-bit memory bus. That's what WDC 65C816 from 1985 does, but it also goes full 16-bit mode as well.

And if you have a 16-bit CPU, you can do all kinds of silly stuff; for instance, you can have 4 16-bit MSRs, let's call them BANK0–BANK3, that would be selected by the two upper bits of a 16-bit address, and would provide top 16 bits for the bus, while the lower 14-bits would come from the original address. That already gives you 30 bits for 1 GiB of addressable physical memory (and having 4 banks available at the same time instead of just 2 is way more comfortable) and nothing stops you from adding yet another 4 16-bit registers BANK0_TOP–BANK3_TOP, to serve as even higher 16 bits of the total address — that'd give you 16+16+14 = 46 bit of physical address (64 TiB) which is only slightly less than what x64 used to give you for many years (48 bits, 256 TiB).

I was trying to get a grasp on what would be pratical.

Even 4MB would take you hours to load from floppies with a 6502.

Terabytes with a 68000 would also be impractical.

> Even 4MB would take you hours to load from floppies with a 6502.

Depends on your clock. Also, you could use some dedicated hardware, like a DMA controller e.g. 8257, or 8237. From 8257's datasheet:

    Speed

    The 8257 uses four clock cycles to transfer byte of
    data. No cycles are lost in the master to master transfer
    maximizing bus efficiency. 2MHz clock input will
    allow the 8257 to transfer at rate of 500K bytes/second.

and I recall 8237 could do even better, if wired and programmed properly.

Hard drivers were available for the 6502. They were expensive ($10k for a 10MB drive as I recall prices came down a lot, but never affordable in the 1980s)

Processing terabytes with a single CPU was impractical, but you could in theory connect it.

The Commodore REU (RAM Expansion Unit) architecture for the C64/C128 allows for up to 16 MiB - 256 banks of 256 addresses in 256 pages.

Due to the lack of support hardware in the C64 (no hardware RAM bank switching/MMU) this memory is not bank switched and then directly addressable by the CPU, it's copied on request by DMA into actual system RAM. But in some sense, a C64 with a 16 MiB REU is a 6502 with 16 MiB RAM.

But yeah, you want CPU addressable RAM with real bank switching. You couldn't really do 16 MiB, you wouldn't want to bank switch the entire 64 KiB memory space. The Commander X16 (a modern hobbyist 6502 computer) supports up to 2 MiB by having hardware capable of switching 256 banks into an 8 KiB window (2 MiB/256 banks = 8 KiB).

Let's say you design something with 32 KiB pages instead -- that seems kind of plausible, depending on what the system does -- you could then do 256*32 = 8 MiB and still have 32 KiB of non-paged memory space available. I think this looks like just about the maximum you would want to do without the code or hardware getting too hairy.

I know someone who - in the 1990s had 5MB connected to his Atari. He had two different expansions, and used all the memory for a RAM disk, as a result his BBS was the most responsive remote system I've ever used - including ssh to the server under my desk (open question, was it really or is this nostalgia?).

The SN74LS610 family chips were specifically designed to do bank-switching memory management like this for 8-bit micros.

Speed certainly wouldn't be there, but capabilities would. Plenty could get done on those old machines — most of it had to do with programmers having the imagination & skill to be able to shoehorn their ideas into spaces they weren't meant to be crammed into.

One memory this project brought to mind for me was a hack I came across which allowed simultaneously running DOS 3.3 & ProDOS on a 128k Apple II, giving each 64k (well, a little less due to overhead) & a way to switch between the two with a simple command. Two programs couldn't run at once, but one could step between the two OSes to run programs made for each pretty seamlessly. If this sort of thing was possible on basic consumer hardware, ten or twenty years of development would have led to many far more interesting & useful things.

nah, something like LLMs wouldnt be possible due to sheer power consumption - abstract (FL)OPs/uW is billions worse than modern tech. I used claude to make me back of a napkin calcs - single LLM prompt in 6502 era tech would be over 3k Eur vs fraction of a cent today, DISRECARDING WALL TIME (which is ridiculously impractical)

> Imagine in steampunk fashion

See The 8-bit Guy regarding what the world would be like if we were still limited to vacuum tubes: https://www.youtube.com/watch?v=mEpnRM97ACQ (video)

Isn't this basically the idea behind collapse os? Chin up! That could still be our future.

Apple XXVgs and Amiga 15,000, I’m digging this alternative.

I think people would just try to make larger chips. You can still do a 32 bit RISC even one the same node as 6502. Its just a bigger chip. Basically like ARM2 or something. Then you can do a multi-core version of that.

I would love to see a future z80 version so I can run C/PM

This may sound absurd, but it was a mental breakthrough for me to realize that all these "what-ifs" (multicore 6502 computers or whatever) are really simple to simulate in software only, with a bespoke simulator, WAY above register transfer level. There is really no need to deal with the peculiarities of FPGAs or Verilog; just write an instruction-level simulator for the ISA you choose (that's really simple for the 6502), make it run several instances for multicore architectures, and there you go for your custom computer.

I mean this as a hint for people who are similarly stuck with RTL tinkering when they actually want to tinker with system architecture.

Amazing

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