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Comment by monster_truck | Hacker News Reader

The extra cache doesn't do a damn thing (maybe +2%)

The lower leakage currents at lower voltages allowed them to implement a far more aggressive clock curve from the factory. That's where the higher allcore clock comes from (+30W TDP)

I'm not complaining at all, I think this is an excellent way to leverage binning to sell leftover cache.

Though if I may complain, Ars used to actually write about such things in their articles instead of speculate in a way that suspiciously resembles what an AI would write.

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> The extra cache doesn't do a damn thing (maybe +2%)

It depends on the task. For some memory-bound tasks the extra cache is very helpful. For CFD and other simulation workloads the benefits are huge.

For other tasks it doesn't help at all.

If someone wants a simple gaming CPU or general purpose CPU they don't need to spend the money for this. They don't need the 16-core CPU at all. The 9850X3D is a better buy for most users who aren't frequently doing a lot of highly parallel work

But consumer product does not support SDCI (only Epyc Turin supports it), so it does not benefit too much if an accelerator is involved.

It's also useful to point out that the use cases and workloads where SDCI are most beneficial are far, far beyond the scope of what anyone will have installed in a Zen rig. Dual 100G networking cards? The cost of both of those damn near buys all of a 9950X3D2 setup.

no, dual 100Gb are not that expensive any more, eg https://www.scan.co.uk/products/2-port-intel-e810-cqda2blk-d... UK retail for gbp349.

It really doesn't. In virtually every case the work is being completed faster than the cache can grow to that size. What little gains are being realized are from not having to wait for cores with access to the cache to become available.

There are some very specific workloads (say simple object detection) that fit into cache and have crazy performance where the value of the cpu will be unbeatable, as the alternative is one of the cache epycs, everywhere else it'll only be small improvement if the software is not purpose made for it

> It really doesn't. In virtually every case the work is being completed faster than the cache can grow to that size.

If your tasks don’t benefit then don’t buy it.

But stop claiming that it doesn’t help anywhere because that’s simply wrong. I do some FEA work occasionally and the extra cache is a HUGE help.

There are also a lot of non-LLM AI workloads that have models in the size range than fit into this cache.

Sorry, what is "CFD" in this context?

https://en.wikipedia.org/wiki/Computational_fluid_dynamics

CFD benefits from cache, but it benefits even more from sustained memory bandwidth, no? A small(ish) chunk of L3 + two channels of DRAM is not going to compete with a quarter as much L3 plus eight channels of DRAM when typical working set sizes (in my experience) are in the tens of gigabytes, is it?

It's very workload dependent. It certainly does more than 2% on many workloads.

See https://www.phoronix.com/review/amd-ryzen-9-9950x3d-linux/10

> Here is the side-by-side of the Ryzen 9 9950X vs. 9950X3D for showing the areas where 3D V-Cache really is helpful:

Coincidentally, it looks they filtered to all benchmarks with differences greater than 2%. The biggest speedup is 58.1%, and that's just 3d vcache on half the chip.

I think GP was saying that the additional 3D cache on this chip compared to the standard x3d isn’t going to do much.

I’m curious to see whether the same benchmarks benefit again so greatly.

> I think GP was saying...

Agree. The article's 2nd para notes "AMD relies on its driver software to make sure that software that benefits from the extra cache is run on the V-Cache-enabled CPU cores, which usually works well but is occasionally error-prone." - in regard to the older, mixed-cache-size chips.

> I'm curious to see...

Yeah - though I don't expect current-day Ars Technica will bother digging that deep. It could take some very specialized benchmarks to show such large gains.

Some of their writers, who are quite excellent, still do. Others just seem to regurgitate press releases with very little useful investigation.

How critical of the lazy writers I am may seem outsized, but I grew up reading and learning from the much better version of Ars -one I used to subscribe to.

I hoping that phoronix will be able to redo the benchmark of the 9950x3D with this new X3D2 variant.

I might even shell out for an upgrade to AM5 and DDR5. On the other hand, my 5900X is still blazing fast.

On AMD the L3 cache is partitioned between the 2 chiplets.

So for 9950X3D half of the cores use a small L3 cache.

For applications that use all 16 cores, the cases where X3D2 provides a great benefit will be much more frequent than for a hypothetical CPU where the same cache increase would have been applied to a unified L3 cache.

The threads that happen to be scheduled on the 2nd chiplet will have a 3 times bigger L3 cache, which can enhance their performance a lot and many applications may have synchronization points where they wait for the slowest thread to finish a task, so the speed of the slowest thread may have a lot of influence on the performance.

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