Building an Open-Source Verilog Simulator with AI

Big caveat:

"Let's be honest about performance. In interpret mode, circt-sim is far too slow for real-world use. Even with the JIT improvements we made, the simulator is still 100-1000x slower than the competition."

The industry needs open source tools so badly. I've told the EDA companies (at DVCon) that the first one to open source their tools would suddenly get 100% market share and that they could monetize the same way Red Hat does. Looks like they better hurry up.