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Part 2 has benchmarks: https://maderix.substack.com/p/inside-the-m4-apple-neural-en...

6.6 FLOPS/W, plus the ability to completely turn off when not in use, so 0W at idle.

But not 38 TOPS that Apple claims, with the weak explanation of

> Apple’s “38 TOPS INT8” is computed as 19 TFLOPS FP16 × 2, following the industry convention of counting INT8 operations as 2× the FP16 rate. But the hardware doesn’t actually execute INT8 operations twice as fast.

Why would Apple follow that convention when the hardware explicitly doesn't seems like a more straight-faced lie that I expect from Apple

You assume the marketing folks actually talk with the hardware folks. More likely its a big game of telephone....

there's an apocryphal story that when one of Apple's chips was nearing 10B transistors, marketing asked the chip folks if they could round it up to 10B for their copy. The chip folks were confounded, and said no they didn't have any uncounted transistors to round it up, and they didn't approve of claiming 10B transistors when it wasn't.

(This was a while ago. I see the M4 is at 28 B)

Which is why I'm all the more surprised that Apple would claim 2x more ANE TOPS than it can really does.

You're off by a factor of a trillion. It's 6.6 TFLOPS/W.

Well, better to be off by that much here than on my next jira ticket size estimate.

thanks

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