NASA uses Mars Helicopter's SoC for rover navigation upgrade
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Imagine a hundred of these exploring Mars semi-autonomously, maybe with LoRa mesh networking, for not a whole lot more money than it cost to send one.
The permanent errors caused by radiation must be identified by periodic self tests. When the permanent damage is in a redundant structure, e.g. as mentioned in TFA when they find some memory bits that are permanently damaged, they must avoid using what is damaged.
Eventually radiation will destroy something that is essential, but until then the Snapdragon CPU should be usable.
Flying a helicopter on Mars was inspiring and useful for scouting, etc. But maybe the best thing coming out of it is undeniable proof that off-the-shelf hardware without radiation hardening is perfectly viable on Mars if you can just reboot it fast enough
The automotive variants allow the use of multiple redundant cores, which check each other for errors. This would allow a much better performance than NASA gets today from a Snapdragon, due to being forced to run multiple times each computation, then to verify that the same results have obtained.
There are off-the-shelf redundant CPUs of this kind, designed for use in cars and other vehicles, i.e. for a goal much closer of what NASA needs than smartphone CPUs.
The design of the electronics for the Mars helicopter was a very low-effort project, because too many people were skeptical about its chances of success. In other circumstances, it could have been done much better.
"..the critical FPGA which is always on for the duration of the mission, the radiation tolerant ProASIC3 is chosen with the military temperature grade (-55 C to 125 C) and -1 speed grade to mitigate the degradation in the propagation delay caused by the total dose radiation. The single-event upset (SEU) is mitigated with triple module redundancy (TMR) in the FPGA design.
...
The FPGA device is a military-grade version of MicroSemi’s ProASIC3L, which uses the same silicon as the radiation-tolerant device from the same family."[0]
The specs from [1] say there is also a specific radiation-tolerant variant.
So it looks like the CPUs themselves have dual lock-stepped cores, and the CPU checks for errors each cycle. If there's an error it flags the FPGA, which switches to the other CPU.
[0] https://rotorcraft.arc.nasa.gov/Publications/files/Balaram_A...
[1] https://ww1.microchip.com/downloads/aemDocuments/documents/F...
The high-level control and data processing is done by a now very old smartphone Snapdragon 801 CPU, which has no redundancy and it runs Linux. That CPU uses 4 custom 32-bit Qualcomm Krait cores, which were extremely fast in comparison with the radiation-hardened CPUs available at that time, but which are very slow in comparison with the current automotive CPUs or smartphone CPUs.
Nowadays there are automotive redundant CPUs, using high-performance automotive-enhanced ARM cores like Cortex-A78AE or Neoverse V3AE, which are far more suitable for a space mission than a smartphone CPU.
Because Snapdragon does not have the right hardware, approximate redundancy is achieved by software, i.e. by running multiple times each algorithm and comparing the results, and also by periodic self tests.
This is better than nothing, but a hardware-redundant CPU would have provided much better performance.