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Comment by Irishsteve | Hacker News Reader

Post a link to the most mainstream tool please. Someone might try to change that world.

While I admire your moxy, you need to understand that a full suite of tools we use to get ASICs designed, verified, laid out and ready for fab cost 5 or 6 figures per license, depending on what you're doing. The very use of the tools themselves, is subject to non-disclosure agreements. So are the details of their pricing.

I do think the status quo will be radically reshaped by an external force one day, but thinking one is going to mount an assault without knowing who the three main EDA vendors are - let alone without real-world ASIC experience - is quixotic.

It is also not obvious to me how the economics of a viable competitor would actually work.

[EDIT: I hope this didn't come across as excessively abrasive. You are quite right - it's an industry that needs shaking up, but its not obvious how to do it. Fresh faces and new ideas would help us at least realize that there is a problem]

Could you talk a little about what the major shortcomings of the current players are?

My biggest gripe would be with the abomination of a language we have for functional design and verification, SystemVerilog.

- It has been developed without public discussion, now that the IEEE has shut down their mailing lists to non-paying entities and persons

- The steering committee are bright, well-meaning individuals... who don't appear to have any language design experience between them, and whose knowledge of programming languages appear to be limited to Verilog, Java and a daring dash of Tcl. They have never seen a feature they didn't think was worth adding as new syntax.

- It retains backward compatibility with Verilog, which was a cool hack in 1983.

- It basically looks like Java with a whole bunch of additional (inconsistent) syntax for stuff that should probably be in a standard library, but...

- It doesn't have a standard library

- Oh, and by Java, I mean Java as it was in 1995. Or at least, it will have sort of the same feature set, once they add interface inheritance - later this year. Yup, 2012.

- Its metaprogramming facilities are weaker than ANSI C, which is why most large ASIC shops end up brewing their own metalanguage syntax, usually by having embedded snippets of Perl or Tcl.

- And this inexpressive, crippled language somehow has a spawling mess of a spec that runs a whopping 1200+ pages.

The entire thing is a train-wreck.

I used Verilog a little bit in college, while studying for my EE degree. It didn't seem like a bad language. It was a weird blend of register transfer-level stuff and C-like pseudocode stuff.

It sounds like Verilog fell prey to the C++ philosophy of language design-- just keep adding anything that sounds remotely like a good idea to the core language. If it interacts poorly with what's already there, that's just too bad.

Unfortunately, new programming languages are NOT a good startup idea, in any field. Also, if people are paying 5 and 6 figures for tools in SystemVerilog, change is going to be slow.

Some of the tools we used in my computer engineering curriculum were HDL Designer from Mentor Graphics and some tools from Xylinx that were similar. If I remember correctly the reps from Caterpillar said they invested in HDL Designer pretty heavily as it was used widely there. I mention Caterpillar specifically because their world headquarters was about an hour and a half down the road and they recruited pretty heavily from UIUC.

HDL Designer was cool but it was pretty outdated looking even 5 years ago when I was at school. It was all motif running on Sparc Solaris boxes.

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