LoongArch is a weird mix of MIPS and RISC-V. There's not much that would be gained by investing a whole bunch into LoongArch that couldn't also be done to RISC-V, if at all.
The 2023 3A6000 already reached the performance of this RISC-V board
We actually don't know a lot about the UR-DP1000 chip, while we do know quite a bit about the 3A6000 because of Chips and Cheese. This makes a thorough analysis of the crimes committed within the core architecture of the UR chip more of speculation than a coherent discussion.
But we do know:
1. The UR-DP1000 does not have any Vector instructions 2. UR only has a 4 way OOO design, while the 3A6k is 6 way OOO 3. The cache architecture of the UR is more complicated, with 4 cores sharing 4MB L3 per cluster (2 clusters total), and a 16MB global L4 where the 3A6k doesn't have this 4. The UR chip doesn't have SMT