Asus ROG laptops are broken by design: a forensic deep dive | Hacker News Reader

Asus ROG laptops are broken by design: a forensic deep dive

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7 pointspdpi4 comments

Many thanks for this entry. Knowing the reason for the shutdown hang is very valuable. It prevents me futzing my brains out and doing damage whilst trying to repair it.

I did experience something odd however. At some point during tweaking various settings, both in the new OS (linux) and BIOS, I was unable to F2 access the BIOS during start. I thought to find the CMOS battery to reset the BIOS but I COULD NOT FIND THE DAMNED THING. So before sending it back to ASUS, I removed the PCIe drive since it had personal info on it.

But booting AFTER removing the PCIe drive gave me access to the BIOS. I thought BIOS boot was independent of hard drive presence?

Anyway, after booting the BIOS I rescued my new machine and only had two screws left over after taking the darn thing apart!

trivia: first boot into linux resulted in "no hd found". Turns out this ASUS BIOS won't detect the linux hd unless you set VMD to disabled which enables AHCI. Thanks for the obfuscation ASUS!

> This issue was reported to ASUS Engineering 24 days ago with full register dumps and forensic analysis. The mismatch persists in the latest firmware.

Bit early to call it broken by design...

It’s a bit… aggressively worded, yes, which does detract from the message. But it was the investigation itself that tickled me. I wish my abilities to debug “why is my laptop crashing” extended to the level of determining that this sort of timing is off.

This looks like LLM slop (not only the writing, but the analysis itself).

To start, it is based on a single machine check. It has little context, but if this was a common problem, I'd expect more data points.

The MC happened 8 hours after the freeze. It's not unusual that a hardware/kernel failure cascades to multiple subsystems so I'd be sceptical that the MC has a direct relationship to the root cause of the freeze.

(Part 13) Why does it quote an Engineering Change Notice rather than a consolidated spec?

(Part 11) LaneErrStatus=0xFFFFFFFF is 32 bits. As far as I know, PCIe x32 is very rare.

(Part 8.4) How is it surprising MMIO isn't included in memory dumps?

(Part 4) How is the definition of a MCE relevant here?

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