It's not really that different from Apple reserving wafer starts on TSMC's next node and so on. It's just that this kind of capacity requirement has rarely shown up in DRAM before. Vendors prefer this kind of capacity reservation over a more variable finished product requirement. It allows them to know that they can build at the bottleneck rather than having to start up more capacity and then having that lie idle while everything downstream in DRAM packaging and DIMM production can't actually consume anything.