Minor nitpick but the video controller has direct access to RAM and when the visible part of the display is being drawn by the video controller, it does cycle-stealing DMA that preempts the CPU.
You can read in depth about it from Steve Chamberlain, the designer of an FPGA low level clone of the Mac Plus here: [0]
By the way but this why the compact Macs have CPU performance of about a 6 MHz 68000 when clocked at almost 8 MHz. About half the time the display is being redrawn. And about half the memory bandwidth is used up at those times.
Bit of a tangent but the Apple II used a similar approach for its video system. As the article notes, the 68K has a prefetch queue. So it's always reading ahead which is what you get from reading an open bus. But the 6502 is a simple CPU without that fancy prefetch queue, so if you read a non-extant address on the Apple II you get what the video system just read and drew in the previous half-cycle. It's possible to sync up the CPU with the video system this way; something otherwise impossible on the Apple II. [1]
[0] https://www.bigmessowires.com/2011/08/25/68000-interleaved-m...
[1] http://www.deater.net/weave/vmwprod/megademo/vapor_lock.html