I feel most people would unless you use some Hard IP for the interface. Like you don't bit-bang PCIe when you feed a wide AXI stream at a few MHz into the PCIe block where it get's serialized and put onto the lanes at the signalling rate (multiple Gigahertz, depending on generation).

I don't have any hands-on experience with FPGAs. I only know about as much about FPGAs as I do about red herring.