Apple A6 Teardown
ifixit.com
ifixit.com
A6 was manufactured at 32 nm, so 30% improvement, and the chip is also 97 sq mm. So another 40% improvement.
Let's say the new architecture brings say 40% IPC improvement for the CPU cores, like A15 cores do over A9 (could be less, could be more).
Then the new cores are also clocked at 1.2 Ghz (according to Anandtech's tests, ifixit doesn't seem to check this, just goes by the rumors), that's another 50% improvement over the old CPU cores.
The last 2 improvements alone could make the CPU's speed 2x over the iPhone 4S's CPU, while the first 2 types of improvements could've been used to introduce a larger GPU (3 cores) and at a higher frequency (thanks to die shrinkage).
"Let's say" ? Surely this is something that can be trivially measured just by running a benchmark. Has one been done? Note that 40% seems pretty optimistic, considering similar bumps in transistor counts in the Intel world generally get about a 10% benefit (you can do better by adding more cores, of course, but squeezing instructions through a pipeline with transistor logic alone is really hard).
Also: your analysis is off. Transistor count scales linearly with die area, but as the square of node size (not quite, as the transistor layout changes between processes, but it's still a linear, not areal metric).
About 1/4 of that can be attributed to the clock frequency.
There's really nothing left but the IPC to attribute the remaining (~75%) gain in performance.
I was hoping for something like a cache-bound CPU test that can look at IPC specifically.
So if the increase from clock speed alone is 50%, that means a 1.5x multiplier, which means the "other" IPC multiplier is somewhere between 1.3x-1.4x (to get 2x over iPhone 4S), which would be on par with Krait and Cortex A15.
Also, when comparing processors running Android vs processors running iOS, it's also important to take note not only of the difference in OS, but also in browsers (related to the browser tests I've seen so far).
* An inductor is a primitive circuit element, like a resistor or capacitor. An ideal inductor maintains the relationship V = L x dI/dt, where V is the voltage across the 2 terminals of the inductor, I is the current through the inductor, and L is the inductance.
* The simplest inductor is a coil of wire. You've probably seen ones that look like this ( http://www.electronicplus.com/images/products/387268.jpg ) on motherboards, power supplies, etc. Inductors are used in power supplies all the time, but also in clocking-related circuits, filters, and other components used in RF devices like the chip referenced in the article.
* In the context of a planar CMOS chip, you can't really build a 3D torus like that, so you build a 2D spiral that approximates a coil ( http://bmf.ece.queensu.ca/mediawiki/index.php/Spiral_Inducto... ). That's called a spiral inductor.
* The horseshoe inductor is just a spiral inductor that only has one loop, and is consequently shaped like a horseshoe. Designers vary the size, spacing, number, and geometry of loops depending on the inductance, parasitic resistance/capacitance, material properties, etc.
Presumably there is some strain in relations between Apple and Samsung, given that they compete in the mobile device market, and the lawsuit over copying designs.
Would Apple be worried that Samsung would be able to glean trade secrets from their custom design of the A6? Would the information provided to Samsung for manufacture of the chip pose this kind of risk? Or would be less like handing off source code, and more like handing off a compiled binary?
http://folklore.org/StoryView.py?story=Nybbles.txt
"The Apple II disk controller, designed six months after the Apple II itself was complete, was Steve Wozniak's crowning achievement. His five chip disk controller card out-performed competitive controllers that were four times as expensive by shifting most of the responsibilities from hardware to software. In Woz's approach, the software was responsible for doing all of the encoding and decoding, head stepping, etc. This allowed Woz to improve the capacity and performance over standard techniques."
http://apple2history.org/history/ah05/
For two weeks, he worked late each night to make a satisfactory design. When he was finished, he found that if he moved a connector he could cut down on feedthroughs, making the board more reliable. To make that move, however, he had to start over in his design. This time it only took twenty hours. He then saw another feedthrough that could be eliminated, and again started over on his design. “The final design was generally recognized by computer engineers as brilliant and was by engineering aesthetics beautiful. Woz later said, ‘It’s something you can only do if you’re the engineer and the PC board layout person yourself. That was an artistic layout. The board has virtually no feedthroughs.’
It's a matter of distance between components on the die, and transistor sizing. At the scale of complex integrated circuits, it's just about guaranteed that an automatic route will do a good job, but stands a good chance of messing a few hotspots up.
I'm not an expert on the algorithms used for automatic routing, but there is some random guessing involved. You can even provide a seed for the random number generator.
More often than not, a hybrid approach is used where the designer gives broad recommendations on where to place components and lets the autorouter go from there.
Then at the end, the designer may go in and tweak some hot spots, or scrap it and start over with a new seed.
I've had times where the auto router for a board gave up because it couldn't complete the routing, ripped everything up and did it by hand. Sure it took longer but the routes were shorter, and I finished routing the board with room to spare.
[1] When I was at Intel the 386 was the new hawtness. The first silicon samples powered up and ran which was awesome but at 'full speed' there were some issues that turned out to be related to a clock signal somewhere between the registers and the ALU. The design engineer replaced a metal feature (typical conductors were done in the metal layer) with a polysilicon version which had the effect of slowing down the propagation speed enough to line up the clocks. (it was fortunate it didn't need to go faster which is harder to do :-) These days the device geometries are so small as to require a lot of analysis which I would not enjoy trying to do by "hand".
"Generally, logic blocks are automagically laid out with the use of advanced computer software. However, it looks like the ARM core blocks were laid out manually—as in, by hand. A manual layout will usually result in faster processing speeds, but it is much more expensive and time consuming. The manual layout of the ARM processors lends much credence to the rumor that Apple designed a custom processor of the same caliber as the all-new Cortex-A15, and it just might be the only manual layout in a chip to hit the market in several years." (emphasis mine)
Even then "several years" is unspecific, and could mean practically anything from the iPhone classic release era (which is basically ancient history by smartphone technology years at this point) to the (not that old) iPhone 4 release era.
As Apple A6 is one of the very few modern chips designed by hand, it's pretty much the latest argument by some of the best chip designers in the industry against automatic routing & layout. It will be interesting to see how it will fare against the machine-designed Cortex A15.