IBM says quantum computing error correction algorithm can run on AMD chips

"IBM lays out clear path to fault-tolerant quantum computing". IBM Quantum Computing Blog. (2025-06). ; 2025 IBM Quantum Roadmap https://www.ibm.com/quantum/blog/large-scale-ftqc

- ( [2506.03094] Tour de gross: A modular quantum computer based on bivariate bicycle codes https://arxiv.org/abs/2506.03094 )

- [2506.01779] "Improved belief propagation is sufficient for real-time decoding of quantum memory" (2025) https://arxiv.org/abs/2506.01779 :

> Abstract: [...] Relay-BP is inherently parallel, enabling rapid low-footprint decoding with FPGA or ASIC real-time implementations, similar to standard BP. A core aspect of our decoder is its enhancement of the standard BP algorithm by incorporating disordered memory strengths. This dampens oscillations and breaks symmetries that trap traditional BP algorithms.

- "QUEKUF: An FPGA Union Find Decoder for Quantum Error Correction on the Toric Code". ACM Transactions on Reconfigurable Technology and Systems (2025) https://dl.acm.org/doi/10.1145/3733239

necst/QUEKUF: "Union Find Decoder for Quantum Error Correction on the Toric Code": https://github.com/necst/QUEKUF

WTF does it even mean to run a quantum error correction algorithm on a (classical) FPGA?