This is a single-cycle, architecture-level simulator with no microarch details or "complex" features (privileged infra, mapped memory, etc). But it is a good starting demo.

BTW, why invent Yet-Another-Toy-Arch(tm)? If a more established architecture is used, existing toolchains can be utilized to produce images for running. Many popular RISC ISAs have "simplified" editions which are void of many complex features, so they hardly need more efforts to implement with respect to this one.