Diamond Thermal Conductivity: A New Era in Chip Cooling | Hacker News Reader

Diamond Thermal Conductivity: A New Era in Chip Cooling

spectrum.ieee.org

204 pointsrbanffy66 comments

Summary:

> Rather than allowing heat to build up, what if we could spread it out right from the start, inside the chip?... To do that, we’d have to introduce a highly thermally conductive material inside the IC, mere nanometers from the transistors, without messing up any of their very precise and sensitive properties. Enter an unexpected material—diamond.

> ... my research group at Stanford University has managed what seemed impossible. We can now grow a form of diamond suitable for spreading heat, directly atop semiconductor devices at low enough temperatures that even the most delicate interconnects inside advanced chips will survive... Our diamonds are a polycrystalline coating no more than a couple of micrometers thick.

> The potential benefits could be huge. In some of our earliest gallium-nitride radio-frequency transistors, the addition of diamond dropped the device temperature by more than 50 °C.

Fifty Celsius is an insane drop.

It sounds like the most important part of the article (and another cool quote) is this:

>Until recently we knew how to grow it only at circuit-slagging temperatures in excess of 1,000 °C.

So basically, the big breakthrough was low-temp growth of a diamond lattice. Very cool they can do it at such a low temperature. It must be a crazy low temp - probably under 100C?

The article says 400C

From the article:

"we were able to find a formula that produced coatings of large-grained polycrystalline diamond all around devices at 400 °C, which is a survivable temperature for CMOS circuits and other devices."

Thanks, not sure how I missed that. Still, a 60% drop in required temp! These gems are truly, truly outrageous.

~50% it helps to do these calculations using the Kelvin scale.

Learnt that in Physics lab.

That makes sense. A direct scale instead of degrees of representation. Thanks for the correction.

It is genuinely impressive to grow thin film polycrystalline diamond at 400C, but my understanding is this temperature is basically at the ceiling of what the circuits will tolerate in the course of manufacturing to still get a good quality device at end of line. Stress tests, anneals, and wafer bakes are usually limited to about 400C - unless the point is to deliberately degrade the chip

Not to say that it can't be done, only that the process window is not very large and the propensity for deleterious carbon soot is very high. Likely this will generate some very fun, highly integrated problem statements before we see this available for sale.

Getting heat out of the chip is such a painful and important struggle. I hope this works on a real process line. Too many benefits on the table to ignore.

Edit: Grammar, clarity

I wonder, in situations like the Raptor lake fiasco or other "overclocked a little too far" scenarios where the circuit degrades to the point the frequency must be reduced to maintain expected stability, that some very small spots on the chip approached that temperature, while the temp sensor read 100C or below (not kicking in thermal throttling when it should've)?

Caveats: My understanding of the Raptor Lake mess is pretty limited, mostly because Intel has been fairly closed lipped on what specific issue caused that. My personal suspicion is that it was a pareto plot's worth of issues. Also, while I do know a few things about this particular topic, I am far from the final authority on it.

My understanding is that point/local resistive heating problems out in the wild tend to drive different failure modes vs the global heating techniques used on the manufacturing line, mostly because the CPU is in active operation, which changes the defect physics. Put another way, likely any particular structure in the CPU would not need to reach 400C to fail - even the small voltages used in these chips coupled with elevated temperature can drive a lot of difficult-to-catch, slow-to-manifest failure modes. Copper metal migration is the classic example of this type of problem, where copper ions slowly migrate under voltage+temperature, causing/propagating voids until finally an open circuit is made. Surprise! your chip no longer works after seeming perfectly fine! Manufacturers try to catch such problems with simulated aging through aggressive temperature and voltage experiments. Intel must have discovered a big gap in their visibility, and then discovered their CPU specs were incompatible with the stated product lifetime without a major re-spec of already sold product. Ouch.

The chip manufacturer also has some capability to make repairs and adjustments ahead of end of line, which should encompass managing some of the issues you refer to. Some big customers might have their own repair capabilities.

Edit: Clarity, trying to better address the question

If growing diamonds is the thermal bottleneck of manufacturing processes, one could imagine a sci-fi future where rather than silicon wafers serving as base matrix material to grow ancillary structures upon, it would instead be diamond wafers that are used to subtractively etch structural scaffoldings, around which silicon-based structures are grown, the diamond scaffolding serving simultaneously as bone and blood vessels for thermal and power conduction as well as mechanical support.

If this can enable practically unlimited 3D stacking of CMOS layers, it could be hugely consequential for computing.

On an unrelated note, I like the writing style of this article a lot. This is how science journalism should be. It reminds me of how Scientific American used to be before it was ruined. Is IEEE Spectrum always like this? I might have to subscribe to the print version. I want articles like this floating around my house for my kids to discover.

Spectrum is typically pretty good, but this article definitely stands out as very well written. I'm guessing that's because it's written by an actual contributor to the research. Nothing beats when those guys can actually unpack an idea simply.

Great science communication. This is another really good Spectrum article that was on HN a while back.

The Tiny Star Explosions Powering Moore’s Law https://spectrum.ieee.org/euv-light-source

That part could get way more compact, precise, reliable and more energy effcicient soon:

https://pubs.aip.org/aip/app/article/10/8/086105/3357991/Ele...

The editors at IEEE Spectrum are very good at improving articles. They also thoroughly fact-check articles. (Source: I wrote a couple of articles for IEEE Spectrum.)

The article and paper don't mention it, but the thermal conductivity of single crystal diamond can be increased another 50% at room temperature by using pure carbon-12. The isotopic uniformity reduces scattering of phonons, which are what transports heat energy in diamond. For a very thin film like this the cost of using isotopically purified carbon shouldn't be that bad.

BTW, the thermal conductivity of C-12 diamond at cryogenic temperature is even higher, reaching something like 41000 W/m K at 104 K.

Isotopically purified silicon has also been considered due to its higher thermal conductivity, but the effect there at room temperature is not nearly as dramatic.

Weirdly, I read UV damage in C-12 diamond is reduced by a factor of 10 vs. natural diamond, I understand because this damage process is mediated by phonons. No relevance to the chip use case (unless UV damage in photolithography could be important?), but I found it interesting.

This is polycrystalline diamond, which probably scatters phonons anyway, so it seems naively like using a single isotope wouldn't help much. But that's definitely an interesting fact and I think you're right that it probably wouldn't add much expense when the amount of material is so small.

I'm not sure that's too dominant? The thermal conductivity reported is close to the natural diamond, so increasing the conductivity of the individual microcrystals could still be significant.

I joked about it last year[0], but before going for isotopically pure diamond they first have to make them single-crystal, the grain boundaries are worse than isotopic impurities.

[0] https://news.ycombinator.com/item?id=39742447

Why not just use the diamond as the semiconductor?

https://www.powerelectronicsnews.com/diamond-semiconductors-...

Edit: Because they are polycrystalline, and produced with a very new and novel technology.

"Our diamonds are a polycrystalline coating no more than a couple of micrometers thick."

As the article you link says:

> The high p-n junction built-in voltage (4.9V, compared to 2.8V in SiC) and short carrier lifetimes limit the advantages of bipolar diamond devices to only ultra-high voltages (> 6kV) and low switching frequencies.

Nobody is thinking about using diamond for the silicon CMOS logic in a computer, though they may replace the gallium arsenide we use for motor control some day.

The author of the subject article goes on to relate:

"Before my lab turned to developing diamond as a heat-spreading material, we were working on it as a semiconductor. In its single-crystal form—like the kind on your finger—it has a wide bandgap and ability to withstand enormous electric fields. Single-crystalline diamond also offers some of the highest thermal conductivity recorded in any material, reaching 2,200 to 2,400 watts per meter per kelvin—roughly six times as conductive as copper. Polycrystalline diamond—an easier to make material—can approach these values when grown thick. Even in this form, it outperforms copper.

"As attractive as diamond transistors might be, I was keenly aware—based on my experience researching gallium nitride devices—of the long road ahead..."

Cue Neal Stephenson’s “the Diamond Age”

Diamond is a wide-bandgap semiconductor; if it can be made to work, it would couplete with GaN and SiC, not silicon.

Assuming this becomes easier and cheaper to do as the technique matures, a different use of this could be to help with cooling solar PV cells. Despite it being desirable (in terms of overall energy output) to put solar panels in places where the sun's energy is felt the strongest, solar panels tend to work the most efficiently when they're cool. By making it easier to efficiently cool solar PV cells, it may help provide a small boost in overall solar output.

Putting on my frowny-faced principal engineer hat: we need someone to do the calculation of cost of manufacturing vs the amount of money saved by increasing energy efficiency.

[flagged]

Heh, my glasses were actually quite dirty when I wrote that.

More seriously: I did see that, and your idea is interesting! My intent was to communicate the minimum threshold we would need to hit to make that future a reality.

Fun fact, diamond has 4x the thermal conductivity of copper.

May our children live to use high-end diamond cookware

I had to look up at what temperature diamonds start to oxidize/burn[0]: Different sources say different things but apparently it's somewhere between 700°C and 900°C (depending on the exact conditions I suppose).

I suppose that's enough for cookware?

[0]: https://m.youtube.com/watch?v=TPyuDY3iq1Q

Gas flames are easily hotter and exposure to flame can start burning below the autoignition temperature.

Maybe it could be used as an inner-layer in multi-layer cookware (like some pans use aluminum today)?

Your lower and is around the melting point of aluminum, that is in wide use in cookware.

Even according to the article: "2,200 to 2,400 watts per meter per kelvin - roughly six times as conductive as copper.". It's way higher than copper in fact. Copper is ~400 W/(m·K)

“If our work continues to succeed as it has, heat will become a far less onerous constraint in CMOS and other electronics too.”

When it matures, you’re right back to the same heat constraint considerations, just with faster chips.

So? You're always going to hit some constraint. Such is the nature of physical reality after all. Advances in the field are all about pushing past the current blockers to the next ones.

"Diamond substrate breakthrough enables faster chips."

> There are hurdles still to overcome. In particular, we still have to figure out a way to make the top of our diamond coatings atomically flat.

Not sure I understand this. Is this a requirement for real-world use? What happens if the outside of the coating isn't atomically flat? What makes this hard to do?

Presumably it's to ensure good contact with the next thermal management layer (heat spreader, heat-sink, etc.)

These are gigantic and interesting questions packed into some pretty tiny boxes :) I will try to capture some of the issues involved.

Caveat: For older processes, built on a larger scale (>1 micron), these kinds of details may not matter, in which you are right to question this point. But if you want to implement on cutting edge manufacturing processes, these details absolutely do matter.

To put this in perspective, in cutting edge process nodes, I've seen senior engineers argue bitterly over ~1 nm in a certain critical dimension. That's (roughly) about 5 atoms across, depending on how much you trust the accuracy of the metrology.

So, if ANY layer isn't "flat" (or otherwise to spec within tolerance), the next layer in the semiconductor patterning stack will tend to translate that bumpiness upward, or cause a deformity in adjacent structure. This is (almost) always bad. These defects cause voids, bad electrical/thermal contacts and characteristics, misshapen/displaced structures, etc, etc

Crystallization in thin-film (especially conformal/gap-filling films) is a tough job which many poor PhD students have slaved over. Poly crystalline material is arguably harder to control in some key ways vs mono crystalline, since you don't have direct control the specific crystal grain orientation and growth direction. That is, some grain orientations will grow quickly, and others growing slowly. You can imagine the challenge then of getting the layer to terminate growth without ending up too jagged on the ~nm scale. After that you also get into the fun world of crystal defects, grain size, and deciding if you need to do some more post-processing (do I risk planarizing?)

Hopefully I have captured some of the pieces involved in an understandable way.

Edit: clarity

All semiconductor manufacturing techniques are based upon precisely flat layers of material that can be stacked and/or drilled into to produce a useful design. All vertical irregularities propogate to the layers above and can cause thinner layers when an upper layer is milled flat

It’s difficult to cmp diamond is the issue I’d assume

This. A quick scan of the wikipedia page for diamond material properties suggests you are very correct. It appears very chemically inert, with some outstanding exceptions: "Resistant to acids, but dissolves irreversibly in hot steel"

https://en.wikipedia.org/wiki/Material_properties_of_diamond

Also, removed/liberated particles of Diamond from the workpiece which failed to fully chemically dissolve into the slurry would then contribute to the abrasive in the slurry. If the slurry abrasive was not also diamond, then that could lead to some serious scratch/gouging of the work surface.

Perhaps not insurmountable, but wow, that sounds like a stiff challenge, especially when accounting for cost.

I wonder if diamond would be machinable with a dry (plasma) etch instead? I am purely speculating here, this is far out of my wheelhouse. But SiO2 is already very chemically inert (though considerably softer vs diamond), but manufacturers regularly dry etch it.

If this can be scaled up, I wonder how useful it would be for use in space for radiative cooling - clearly, you can see I’m thinking of diamond skinned space-craft hulls - how cool is that!

I think cooling in a chip vs cooling in space are two orthogonal problems. In a chip, the problem is getting the heat to the heatsink where it can be efficiently dissipated into the much larger heatsink of the surrounding environment. In space, the problem is that the only way to dissipate heat is thermal radiation because you're in a vacuum.

> only way to dissipate heat is thermal radiation

Well, besides ejecting the heat as propellent (probably water?).

Thermal radiation is probably the best way, propellent runs out eventually.

If we could stack chips, what's the theoretical density there? How thin could the layers actually be?

If a chip were to be stacked as tall as it was wide, are we talking 10x, 100x, 100,000x?

I guess for N stacks you're still paying N chips worth of wafer, and Nx the amount of defects.

NAND flash memory chips these days are manufactured with low hundreds of layers of memory cells on each die, so they're probably some of the thickest individual dies. They are commonly packaged with up to 16 dies per package, usually in one or two stacks. Those packages are usually under 3mm thick.

The packaging usually has the stacked dies offset in a staircase pattern so that the contacts at the edge are exposed for every die. The alternative is through-silicon vias (TSVs), which theoretically would allow stacking until you have a mass of chips that is roughly a cube, but achieving that without having a defective connection somewhere in the stack is approximately impossible.

When you use Through-Silicon Vias (TSVs) to connect the layers together, you would start to end up with scaling limits, similar to the problems of elevators in skyscrapers: the more layers you have, the higher the density of TSVs would (presumably) be required.

This is probably not an issue for thermal TSVs, because of the heat spreader layer between each silicon layer, but it would become an issue for power TSVs, as each layer would (presumably) require an independent supply of power.

"Diamond Blankets Will Keep Future Chips Cool" (2025) https://spectrum.ieee.org/diamond-thermal-conductivity

Are diamond blankets necessary for cooling graphene semiconductors, which are much less thermally wasteful?

Reminds me of this paper:

"Oxygen-assisted monodisperse transition-metal-atom-induced graphite phase transformation to diamond: a first-principles calculation study"

I think it's pay-walled unfortunately. https://pubs.rsc.org/en/content/articlelanding/2024/ta/d4ta0...

Ah, inside the chip. Diamond heat spreaders outside the chip are known.[1]

Next, a diamond layer every few layers in 3D chips?

[1] https://www.alibaba.com/product-detail/Thermal-Management-Gr...

No longer in that industry, but I worked on one of the first generation of semiconductor equipment for production when GAN first started picking up. Took about a decade before we saw it prevalent in consumer electronics. While this is interesting, I don’t see why DLC process won’t do something similar to this paper?

DLC (diamond-like carbon) generally lacks long-range crystalline order. It's thermal conductivity is quite low.

Using diamond as a thermal conductor is already in production: https://www.df.com/diamond-wafer

Fun fact: we already use diamonds in some thermal pastes, and they do perform pretty well, but not chart toppers.

>But with great power comes great…heat!

I confess to being a nerd that appreciates this “joke”

15 years ago a friend of mine was doing his PhD in laser physics and he was using diamonds to make a component cool faster. So the idea may be new in the chips space, but not new in general.

paper: https://www.mdpi.com/2073-4352/9/10/498

Sure sure but is this viable in a market scenario in my lifetime? Otherwise I don’t care. ;-)

I don’t want to get my hopes up like graphene did and then get disappointed again.

But Graphene is being used already

it was supposed to revolutionize the world ...

I can't wrap my head around possible yields, as the method relies on diamond crystals forming in the heat-conducting pillars within the chip, so if the process less than perfect - it can be a source of delayed failure from termal issues within the chip. It also look like a heat-conducting grid would further decrease usable space and the whole wafer needs to be designed around it.

That said, mentioned temperature gains are absolutely and utterly insane even if they come with some high-frequency issues.

Oh man, the integrated problems this will cause for the manufacturing engineers will be of nightmare level. You wont really get to properly test how well you made the heat pipe network until end of line! Hopefully they will be able to drum up some inline metrology to test the heat pipes before then...

This on top of all the through-silicon-vias and backside power delivery would make even the crustiest of engineers weep...

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