I recall reading about a project at CERN to design a 12bit ADC chip that could sample at tens of GHz, maybe 50 or more.
I was perplexed at how they could achieve this.
Turned out it was the same we programmers do. Parallel processing.
They had taken a 12bit SAR unit which ran at like MHz rates, and just cloned it many times. They then had a large analog multiplexer in front to route the signal to the active ADC unit in a round-robin fashion.
That takes a lot of chip real-estate, and the analog muxer had to be carefully designed.
For a simpler approach to speed there is Flash ADCs[1], which kinda brute-force it.
For precision I know multi-slope ADCs[2] are often used.
Sadly I don't know much about the history, and would also love to learn more about it. Bound to be some fascinating stories there.
[1]: https://en.wikipedia.org/wiki/Flash_ADC
[2]: https://www.analog.com/media/en/training-seminars/tutorials/...