Often but not always. For most newer FPGAs, routing is the main source of delay on the critical path, not logic. So if the synthesis tool lowers the logic depth, but does so in a way that increases the distance the signal must travel on the chip, it likely won't help FMax.

This can be caused by increased logic usage, if the synthesis tool must create significantly more LUTs to reduce the critical path. This may make it harder to place the logic on the critical path close together, increasing the routing delay.

Additionally, if the synthesis tool replaces something with a dedicated routing path (most FPGAs have dedicated routing for carries, some may have dedicated routing for local connections in a CLB or between CLBs). These dedicated routing connections usually have a lower delay than the general purpose routing network, potentially increasing delay

The figures they have listed look promising though, they're lower or comparable to the commercial tools in terms of resource usage, with lower or comparable logic depths. They do however not have support for things like carry chains, which may potentially make some things like adders slower than the other tools.