Also looking to their full stack it seem they use VPR/VTR instead of nextpnr for routing. That seems like a backwards choice.
I can't speak for them, so I'm not sure, but I feel like new FPGA suppliers coming around having open source tooling being the default is something that the authors of Yosys would like.
Zero ASIC even credited the original authors in the press release and released the source code, which they didn't need to do. If you release your code under a permissive license, like Yosys did, a company taking it and selling a closed source version of it is something you are allowing. If that's not something you want, choose a different license.
In essence this is something like 99% yosys + 1% their own sauce. Yet they market it as 99% their own sauce + 1% yosys.
They start out by describing all the work that has been done by other people to make open source synthesis possible.
Then they say they've added some well known, industry standard optimizations to the existing open source tools. In addition, they made use of the abc tool in a way that maybe wasn't being done much before.
My view is that if you think someone taking your software, changing some parts, and releasing it under a different name (while still giving you credit in an about section) leaves a bad taste in your mouth, don't release your software with a permissive license. You are explicitly giving permission for someone to do this.
I don't like companies doing this, so I tend to release under GPL. Even then, I'm happy for someone to rebrand and sell it, as long as the source is still shared. I gave them permission to do that.
Don't give someone permission to do something, and then say it's in bad taste when they do that thing.
I don't agree that that kind of permission means you're not allowed to have a bad taste in your mouth. But even if I did agree, that argument only applies to the developer. You are not talking to the developer. We as third parties are fully allowed to complain.
That said, this work is important, you do need it to get your FPGA running. And from the table, the reported optimizations look good (though I haven’t dug into them in detail). Still, describing it as “a synthesis suite” when it’s really “a plugin that adds FPGA support and a few optimizations to Yosys” does indeed leave me with a bad taste in my mouth.
Of course, you don’t have to agree with me. It’s clear from other comments that not everyone does, and that’s totally fine.