But: 99.9% of the people forget about setting the routing constraints/rules so the results turn out to be very bad. Even professionals forget about this.
Lots of things also cannot be auto-routed as you have to work around of details. Usually high-frequency DCDC converters belong into that region for example.
As a beginner these are no tools for you as you cannot judge if they are creating extremely bad designs or what will work. Stick super close to reference designs from datasheets and there will be a good chance that they will work just fine.
Would love auto routing if it was good; routing is tedius, and on cramped PCBs, can be frustrating and make your designs high-inertia to change.
Incidentally, team 6+ layers! Makes routing easier.
Use the completed traces and part locations (complete with human post adjustments and all) as labels and the bare connectivity graph + "constraints" in some form as inputs.
Of course, as with all machine learning projects, the interface is deceptively simple but gives you no information how well the system can work or whether it can work at all...
What's not solved is setting up constraints on signals.
Now if you still want to do this anyway, I'd suggest building an autorouter and automatically generating custom parts with both standard and generated footprints, place them randomly on a PCB with a random number of layers, then autoroute it with a conventional algorithm and there is your dataset.
If you are talking about a typical hobbyist board with very low frequency switching, the problem is relatively simple, particularly if you allow more than two layer boards. Even there you can create massive problems if you do power distribution wrong.
On the other hand, if you are trying to do something with high frequencies, the problem will be much more difficult. For example, many high speed analog-digital converters use low voltage differential signalling (LVDS) to move data around. Such signals are very sensitive to bad routing since they must be kept very near each other (to avoid creating an inductive loop sensitive to external signals) and must have the same length (to retain common mode rejection). Similarly, RF amplifiers will often oscillate badly or have much lower bandwidth if laid out incorrectly.
Second, you're describing netclasses. Every EDA package has this feature. You have to click one extra box when setting up your symbols.
LLM would need to layout and route while board own. We would probably need diffusion or agentic solution where board can be simulated in RL loop.