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Comment by oakwhiz | Hacker News Reader

Were the lanes engineered for 5.0? Maybe this is a signal integrity issue.

The way product segmentation works in this market it’s practically certain they’re physically identical to the board that supports 5 and the only difference is firmware locks and marketing.

PCIe 5 is 32 GT/s (~4GB/s) per lane, and of course double of that of PCIe 4.

It's a crazy rate that can't be trivial to achieve.

It seems pretty worrying, since PCIe 6 for the first time couldn't double the operating frequency and it's not likely to be possible in the feature for traditional copper lanes. I haven't heard how DDR6 will solve this issue. PAM or not PAM?

Having some PCB experience, I disagree. Targeting higher specs like PCIe 5.0 usually requires more expensive PCB materials and tighter qualifications at the test stage.

If the boards were only being tested to PCIe 4.0 (their official spec) then you can't guarantee they perform the same as SKUs targeting PCIe 5.0.

You can't notice these differences with your eyes.

I'm not sure a PCB of such size can be made (without making the PCB actually more expensive) partially with worse and better materials, since the board does support four PCIe 5.0 lanes. The question is how much cheaper would it be to route the 16 lanes only for 4.0 speed rating.

> since the board does support four PCIe 5.0 lanes

The better materials are necessary for longer traces. You can’t make simple comparisons like this

This motherboard already supports PCIE 5.0 for NVME, so it's likely the board stack up is plenty sufficient for PCIE 5.0.

The differential impedance is also identical for PCIE 4.0/5.0 so again, likely not a physical difference issue.

Which basically suggests that the routed the 4.0 lanes much sloppier than 5.0.

It’s not that simple. You could get PCIe 5.0 working on the cheapest FR-4 board if you kept trace lengths short enough.

The trace lengths matter a lot, among other things. You can’t draw conclusions like this.

The general advice is 5 mils Intra-Pair and no specific requirement for Inter-Pair. These follow the same engineering guidelines as PCIe 4.0, with identical impedance and coupling. As far as I can tell, there are no significant differences, aside from PCIe 5.0 having smaller theoretical margins. Even then, the 5 mils spec is likely overkill for both.

From what I’ve read, a well-designed PCB that supports PCIe 4.0 should also meet PCIe 5.0 requirements electrically and for signaling. I suspect the issue may be related more to power delivery or EMC than to trace layout or stack-up. Alternatively, it could just be an AMD policy decision to limit PCIe 5.0 support on this chipset variant, rather than a design flaw.

> I suspect the issue may be related more to power delivery or EMC than to trace layout or stack-up.

Power delivery shouldn't be an issue, the slot power limits haven't changed afaik, max is 75W for an x16 card since the beginning.

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